{"id":"https://openalex.org/W2044534563","doi":"https://doi.org/10.1109/apccas.2014.7032765","title":"A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs","display_name":"A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs","publication_year":2014,"publication_date":"2014-11-01","ids":{"openalex":"https://openalex.org/W2044534563","doi":"https://doi.org/10.1109/apccas.2014.7032765","mag":"2044534563"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2014.7032765","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2014.7032765","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048571648","display_name":"Koichi Fujiwara","orcid":null},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Koichi Fujiwara","raw_affiliation_strings":["Dept. of Computer Science and Communications Engineering, Waseda University","Dept. of Computer Science and Communications Engineering,, Waseda University"],"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science and Communications Engineering, Waseda University","institution_ids":["https://openalex.org/I150744194"]},{"raw_affiliation_string":"Dept. of Computer Science and Communications Engineering,, Waseda University","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103232606","display_name":"Shinya Abe","orcid":"https://orcid.org/0000-0002-4353-7882"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shinya Abe","raw_affiliation_strings":["Dept. of Computer Science and Communications Engineering, Waseda University","Dept. of Computer Science and Communications Engineering,, Waseda University"],"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science and Communications Engineering, Waseda University","institution_ids":["https://openalex.org/I150744194"]},{"raw_affiliation_string":"Dept. of Computer Science and Communications Engineering,, Waseda University","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002692556","display_name":"Kazushi Kawamura","orcid":"https://orcid.org/0000-0002-0795-2974"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kazushi Kawamura","raw_affiliation_strings":["Dept. of Computer Science and Communications Engineering, Waseda University","Dept. of Computer Science and Communications Engineering,, Waseda University"],"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science and Communications Engineering, Waseda University","institution_ids":["https://openalex.org/I150744194"]},{"raw_affiliation_string":"Dept. of Computer Science and Communications Engineering,, Waseda University","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061982025","display_name":"Masao Yanagisawa","orcid":"https://orcid.org/0000-0002-5168-3214"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masao Yanagisawa","raw_affiliation_strings":["Dept. of Computer Science and Communications Engineering, Waseda University","Dept. of Computer Science and Communications Engineering,, Waseda University"],"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science and Communications Engineering, Waseda University","institution_ids":["https://openalex.org/I150744194"]},{"raw_affiliation_string":"Dept. of Computer Science and Communications Engineering,, Waseda University","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087516286","display_name":"Nozomu Togawa","orcid":"https://orcid.org/0000-0003-3400-3587"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Nozomu Togawa","raw_affiliation_strings":["Dept. of Computer Science and Communications Engineering, Waseda University","Dept. of Computer Science and Communications Engineering,, Waseda University"],"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science and Communications Engineering, Waseda University","institution_ids":["https://openalex.org/I150744194"]},{"raw_affiliation_string":"Dept. of Computer Science and Communications Engineering,, Waseda University","institution_ids":["https://openalex.org/I150744194"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5048571648"],"corresponding_institution_ids":["https://openalex.org/I150744194"],"apc_list":null,"apc_paid":null,"fwci":0.613,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.68919638,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"244","last_page":"247"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9392824172973633},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9073147773742676},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.8489221930503845},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7870601415634155},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7582561373710632},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7102953791618347},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5098296999931335},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.47406095266342163},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4568016231060028},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.43178704380989075},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4208608567714691},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.410087525844574},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.386577308177948},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36866647005081177},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.3483670949935913},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32098278403282166},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.21136480569839478},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.16102871298789978},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11653608083724976}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9392824172973633},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9073147773742676},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.8489221930503845},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7870601415634155},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7582561373710632},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7102953791618347},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5098296999931335},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.47406095266342163},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4568016231060028},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.43178704380989075},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4208608567714691},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.410087525844574},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.386577308177948},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36866647005081177},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.3483670949935913},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32098278403282166},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.21136480569839478},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.16102871298789978},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11653608083724976},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2014.7032765","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2014.7032765","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5099999904632568}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2003610890","https://openalex.org/W2007252437","https://openalex.org/W2047631674","https://openalex.org/W2137966900","https://openalex.org/W2150282626","https://openalex.org/W2171413119","https://openalex.org/W4235515009","https://openalex.org/W4235923234","https://openalex.org/W6682184148"],"related_works":["https://openalex.org/W2120659218","https://openalex.org/W2166021916","https://openalex.org/W1903431847","https://openalex.org/W1994884893","https://openalex.org/W1839177134","https://openalex.org/W3141861494","https://openalex.org/W2161004825","https://openalex.org/W3149874529","https://openalex.org/W2004001588","https://openalex.org/W2080729117"],"abstract_inverted_index":{"Recently,":[0],"high-level":[1],"synthesis":[2],"(HLS)":[3],"techniques":[4],"for":[5,24,47],"FPGA":[6,25,51,95],"designs":[7,96],"are":[8],"required":[9],"in":[10,65],"various":[11],"applications":[12],"such":[13],"as":[14],"computerized":[15],"stock":[16],"tradings":[17],"and":[18,33,83,107],"reconfigurable":[19],"network":[20],"processings.":[21],"In":[22,38,67],"HLS":[23,45],"designs,":[26],"we":[27,41,59,73],"need":[28],"to":[29,69,105,112],"consider":[30,62],"module":[31,63],"floorplan":[32,64],"reduce":[34,70],"multiplexer's":[35,71],"cost":[36],"concurrently.":[37],"this":[39],"paper,":[40],"propose":[42,74],"a":[43],"floorplan-aware":[44],"algorithm":[46,92],"multiplexer":[48],"reduction":[49],"targeting":[50],"designs.":[52],"By":[53],"utilizing":[54],"distirbuted-register":[55],"architectures":[56],"called":[57,79],"HDR,":[58],"can":[60,93],"easily":[61],"HLS.":[66],"order":[68],"cost,":[72],"two":[75],"novel":[76],"binding":[77,82],"methods":[78],"datapath-oriented":[80,84],"scheduling/FU":[81],"register":[85],"binding.":[86],"Experimental":[87],"results":[88],"demonstrate":[89],"that":[90],"our":[91],"realize":[94],"which":[97],"reduces":[98],"the":[99,116],"number":[100],"of":[101],"slices":[102],"by":[103,110],"up":[104,111],"47%":[106],"circuit":[108],"delay":[109],"16%":[113],"compared":[114],"with":[115],"conventional":[117],"approach.":[118]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2015,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}