{"id":"https://openalex.org/W2102456816","doi":"https://doi.org/10.1109/apccas.2010.5774997","title":"A low-latency GALS interface implementation","display_name":"A low-latency GALS interface implementation","publication_year":2010,"publication_date":"2010-12-01","ids":{"openalex":"https://openalex.org/W2102456816","doi":"https://doi.org/10.1109/apccas.2010.5774997","mag":"2102456816"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2010.5774997","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2010.5774997","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100855206","display_name":"Yuan-Teng Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Yuan-Teng Chang","raw_affiliation_strings":["Department of Computer Science, National Chiao Tung University, HsinChu, Taiwan","Department of Computer Science; National Chiao Tung University; Hsinchu; Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Chiao Tung University, HsinChu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Department of Computer Science; National Chiao Tung University; Hsinchu; Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052457201","display_name":"Wei-Che Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wei-Che Chen","raw_affiliation_strings":["Department of Computer Science, National Chiao Tung University, HsinChu, Taiwan","Department of Computer Science; National Chiao Tung University; Hsinchu; Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Chiao Tung University, HsinChu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Department of Computer Science; National Chiao Tung University; Hsinchu; Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005741991","display_name":"Hung-Yue Tsai","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hung-Yue Tsai","raw_affiliation_strings":["Department of Computer Science, National Chiao Tung University, HsinChu, Taiwan","Department of Computer Science; National Chiao Tung University; Hsinchu; Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Chiao Tung University, HsinChu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Department of Computer Science; National Chiao Tung University; Hsinchu; Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059489310","display_name":"Wei-Min Cheng","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148468","display_name":"Industrial Technology Research Institute","ror":"https://ror.org/05szzwt63","country_code":"TW","type":"nonprofit","lineage":["https://openalex.org/I4210148468"]},{"id":"https://openalex.org/I142066694","display_name":"ITRI International","ror":"https://ror.org/04wwsbd59","country_code":"US","type":"facility","lineage":["https://openalex.org/I142066694"]}],"countries":["TW","US"],"is_corresponding":false,"raw_author_name":"Wei-Min Cheng","raw_affiliation_strings":["Information & Communications Research Laboratories, Industrial Technology and Research Institute, HsinChu, Taiwan","Information and Communications Research Lab, Industrial Technology Research Institute, Hsinchu, Taiwan#TAB#"],"affiliations":[{"raw_affiliation_string":"Information & Communications Research Laboratories, Industrial Technology and Research Institute, HsinChu, Taiwan","institution_ids":["https://openalex.org/I4210148468"]},{"raw_affiliation_string":"Information and Communications Research Lab, Industrial Technology Research Institute, Hsinchu, Taiwan#TAB#","institution_ids":["https://openalex.org/I142066694"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034825040","display_name":"Chang-Jiu Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I13521601","display_name":"Yu Da University","ror":"https://ror.org/03bej0y93","country_code":"TW","type":"education","lineage":["https://openalex.org/I13521601"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chang-Jiu Chen","raw_affiliation_strings":["Department of Multimedia and Game Science, Yu Da University, Miaoli, Taiwan","Dept. of Multimedia & Game Sci., Yu Da Univ., Miaoli, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Multimedia and Game Science, Yu Da University, Miaoli, Taiwan","institution_ids":["https://openalex.org/I13521601"]},{"raw_affiliation_string":"Dept. of Multimedia & Game Sci., Yu Da Univ., Miaoli, Taiwan","institution_ids":["https://openalex.org/I13521601"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111880499","display_name":"Fu-Chiung Cheng","orcid":null},"institutions":[{"id":"https://openalex.org/I65196183","display_name":"Tatung University","ror":"https://ror.org/030m18266","country_code":"TW","type":"education","lineage":["https://openalex.org/I65196183"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Fu-Chiung Cheng","raw_affiliation_strings":["Department of Computer Science and Engineering, Tatung University, Taipei, Taiwan","Dept. of Comput. Sci. & Eng., Tatung Univ., Taipei, Taiwan#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Tatung University, Taipei, Taiwan","institution_ids":["https://openalex.org/I65196183"]},{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., Tatung Univ., Taipei, Taiwan#TAB#","institution_ids":["https://openalex.org/I65196183"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5100855206"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.7491,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.73643635,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"5","issue":null,"first_page":"1183","last_page":"1186"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7266332507133484},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5708472728729248},{"id":"https://openalex.org/keywords/low-latency","display_name":"Low latency (capital markets)","score":0.5301554799079895},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.505570650100708},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4451283812522888},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3494386374950409},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3105052709579468},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2039756178855896},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09147775173187256}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7266332507133484},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5708472728729248},{"id":"https://openalex.org/C46637626","wikidata":"https://www.wikidata.org/wiki/Q6693015","display_name":"Low latency (capital markets)","level":2,"score":0.5301554799079895},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.505570650100708},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4451283812522888},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3494386374950409},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3105052709579468},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2039756178855896},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09147775173187256},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2010.5774997","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2010.5774997","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.4699999988079071,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1609287256","https://openalex.org/W1943426535","https://openalex.org/W2057144245","https://openalex.org/W2099777845","https://openalex.org/W2117897741","https://openalex.org/W2121914493","https://openalex.org/W2170879979","https://openalex.org/W2487142227","https://openalex.org/W2534012653","https://openalex.org/W3210523556","https://openalex.org/W6675078677","https://openalex.org/W6802779965"],"related_works":["https://openalex.org/W2418291489","https://openalex.org/W2068121105","https://openalex.org/W3205411230","https://openalex.org/W4286899009","https://openalex.org/W9168048","https://openalex.org/W4300849822","https://openalex.org/W4376480820","https://openalex.org/W3155891479","https://openalex.org/W3029351463","https://openalex.org/W4308600690"],"abstract_inverted_index":{"With":[0],"the":[1,10,24,59,68,96,111,129,143,170,181,205],"VLSI":[2,13],"technology":[3],"improving":[4],"rapidly,":[5],"SoC":[6,30],"has":[7],"been":[8],"becoming":[9],"most":[11,26],"important":[12,27,38],"application.":[14],"However,":[15,128],"clock":[16,193],"distribution":[17],"and":[18,157,168],"low":[19],"power":[20],"have":[21],"already":[22],"become":[23],"two":[25],"issues":[28],"in":[29,165],"design.":[31],"In":[32,150,195],"addition,":[33,196],"it's":[34,63],"also":[35,178,198],"a":[36,122,155],"very":[37],"issue":[39],"to":[40,66,141],"integrate":[41],"IPs":[42],"that":[43,180],"can":[44,80,98,113,183],"perform":[45,99],"operations":[46,100],"correctly":[47,185],"with":[48,71,89,101,163,172,186,190],"different":[49,108,126,192],"clocks.":[50],"Asynchronous":[51],"circuits":[52,70],"may":[53,134],"resolve":[54],"these":[55],"problems":[56],"by":[57],"removing":[58],"\u201cclock\u201d":[60],"signal.":[61],"But":[62],"too":[64],"hard":[65],"implement":[67],"whole":[69],"asynchronous":[72,90,117],"circuit.":[73],"The":[74,105,119],"GALS":[75,120,132,146,161],"(Globally-Asynchronous":[76],"Locally-Synchronous)":[77],"design":[78,88,171],"methodology":[79],"balance":[81],"this":[82,151],"problem":[83],"via":[84,116],"separating":[85],"each":[86,93],"synchronous":[87],"interface.":[91],"Thus,":[92],"part":[94],"of":[95,110,131,145],"circuit":[97,112],"its":[102],"own":[103],"clock.":[104],"communication":[106,124],"between":[107,125],"parts":[109],"be":[114],"achieved":[115],"channels.":[118],"provides":[121],"reliable":[123],"modules.":[127],"latency":[130,144],"interface":[133,147],"cause":[135],"performance":[136],"degradation":[137],"seriously.":[138],"Thus":[139],"how":[140],"reduce":[142],"is":[148],"significant.":[149],"paper,":[152],"we":[153,197],"implemented":[154],"small":[156],"simple":[158],"stretchable-clock":[159],"based":[160],"wrapper":[162,182],"low-latency":[164],"Verilog":[166],"HDL":[167],"synthesized":[169],"TSMC":[173],"0.13\u03bcm":[174],"cell":[175],"library.":[176],"We":[177],"showed":[179],"operate":[184,189],"modules":[187],"which":[188],"great":[191],"frequencies.":[194],"recommend":[199],"adding":[200],"FIFO":[201],"storage":[202],"element":[203],"on":[204],"transmission":[206],"path.":[207]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
