{"id":"https://openalex.org/W2160574794","doi":"https://doi.org/10.1109/apccas.2010.5774940","title":"Low power level shifter and combined with logic gates","display_name":"Low power level shifter and combined with logic gates","publication_year":2010,"publication_date":"2010-12-01","ids":{"openalex":"https://openalex.org/W2160574794","doi":"https://doi.org/10.1109/apccas.2010.5774940","mag":"2160574794"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2010.5774940","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2010.5774940","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5114228395","display_name":"Ko\u2010Chi Kuo","orcid":null},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Ko-Chi Kuo","raw_affiliation_strings":["Department of Computer Science and Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I142974352"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065232672","display_name":"Sheng-Quane Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Sheng-Quane Chen","raw_affiliation_strings":["Department of Computer Science and Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I142974352"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5114228395"],"corresponding_institution_ids":["https://openalex.org/I142974352"],"apc_list":null,"apc_paid":null,"fwci":0.2886,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.65999826,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"324","last_page":"327"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.8503798246383667},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6951699256896973},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6257576942443848},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6027402281761169},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5761533379554749},{"id":"https://openalex.org/keywords/pull-up-resistor","display_name":"Pull-up resistor","score":0.5731164216995239},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5482039451599121},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5261473059654236},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.501727819442749},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.49289488792419434},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.48542413115501404},{"id":"https://openalex.org/keywords/emphasis","display_name":"Emphasis (telecommunications)","score":0.4662166237831116},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4525333344936371},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.44808968901634216},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.32552558183670044}],"concepts":[{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.8503798246383667},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6951699256896973},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6257576942443848},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6027402281761169},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5761533379554749},{"id":"https://openalex.org/C61818909","wikidata":"https://www.wikidata.org/wiki/Q1987617","display_name":"Pull-up resistor","level":5,"score":0.5731164216995239},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5482039451599121},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5261473059654236},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.501727819442749},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.49289488792419434},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.48542413115501404},{"id":"https://openalex.org/C177454536","wikidata":"https://www.wikidata.org/wiki/Q578290","display_name":"Emphasis (telecommunications)","level":2,"score":0.4662166237831116},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4525333344936371},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.44808968901634216},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.32552558183670044},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2010.5774940","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2010.5774940","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8399999737739563,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1586205518","https://openalex.org/W2058996914","https://openalex.org/W2121219717","https://openalex.org/W2534854547","https://openalex.org/W6635041956","https://openalex.org/W6677841484"],"related_works":["https://openalex.org/W2171566066","https://openalex.org/W2114346412","https://openalex.org/W2580743037","https://openalex.org/W127821896","https://openalex.org/W2152533674","https://openalex.org/W2100080062","https://openalex.org/W2127519131","https://openalex.org/W1593138522","https://openalex.org/W2112242076","https://openalex.org/W4242766712"],"abstract_inverted_index":{"As":[0],"the":[1,37,41,44,47,61,72,84],"portable":[2],"electronic":[3],"products":[4],"have":[5],"being":[6],"used":[7],"extensively,":[8],"many":[9],"complex":[10],"logic":[11,64],"and":[12],"mathematic":[13],"functions":[14],"need":[15,31],"to":[16,69],"be":[17],"operated":[18],"at":[19],"low":[20,24],"supply":[21,33],"voltage":[22],"for":[23],"power":[25,85],"requirement.":[26],"Different":[27],"function":[28],"blocks":[29],"may":[30],"different":[32],"voltages":[34],"based":[35],"on":[36,43],"performance":[38],"requirements.":[39],"With":[40],"emphasis":[42],"efficiency":[45],"in":[46,83,92],"transistor":[48],"level,":[49],"a":[50],"novel":[51],"level":[52],"shifter":[53],"is":[54,90],"proposed.":[55],"The":[56,88],"proposed":[57,73],"designs":[58],"embedded":[59],"within":[60],"conventional":[62],"digital":[63],"gates":[65],"are":[66],"investigated.":[67],"Compared":[68],"other":[70],"counterparts,":[71],"design":[74,89],"can":[75],"achieve":[76],"an":[77],"average":[78],"of":[79],"7":[80],"times":[81],"smaller":[82],"delay":[86],"product.":[87],"implemented":[91],"TSMC":[93],"90nm":[94],"1P9M":[95],"process.":[96]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
