{"id":"https://openalex.org/W2171381267","doi":"https://doi.org/10.1109/apccas.2008.4746385","title":"A technique of automatic monitor generation based on FSM","display_name":"A technique of automatic monitor generation based on FSM","publication_year":2008,"publication_date":"2008-11-01","ids":{"openalex":"https://openalex.org/W2171381267","doi":"https://doi.org/10.1109/apccas.2008.4746385","mag":"2171381267"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2008.4746385","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2008.4746385","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001713932","display_name":"Duoli Zhang","orcid":null},"institutions":[{"id":"https://openalex.org/I16365422","display_name":"Hefei University of Technology","ror":"https://ror.org/02czkny70","country_code":"CN","type":"education","lineage":["https://openalex.org/I16365422"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zhang Duoli","raw_affiliation_strings":["Institute of VLSI Design, Hefei University of Technology, Hefei, China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Hefei University of Technology, Hefei, China","institution_ids":["https://openalex.org/I16365422"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100553276","display_name":"Yukun Song","orcid":null},"institutions":[{"id":"https://openalex.org/I16365422","display_name":"Hefei University of Technology","ror":"https://ror.org/02czkny70","country_code":"CN","type":"education","lineage":["https://openalex.org/I16365422"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Song Yukun","raw_affiliation_strings":["Institute of VLSI Design, Hefei University of Technology, Hefei, China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Hefei University of Technology, Hefei, China","institution_ids":["https://openalex.org/I16365422"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103664617","display_name":"Du Gaoming","orcid":null},"institutions":[{"id":"https://openalex.org/I16365422","display_name":"Hefei University of Technology","ror":"https://ror.org/02czkny70","country_code":"CN","type":"education","lineage":["https://openalex.org/I16365422"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Du Gaoming","raw_affiliation_strings":["Institute of VLSI Design, Hefei University of Technology, Hefei, China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Hefei University of Technology, Hefei, China","institution_ids":["https://openalex.org/I16365422"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5097669916","display_name":"Zhai Yuanjie","orcid":null},"institutions":[{"id":"https://openalex.org/I16365422","display_name":"Hefei University of Technology","ror":"https://ror.org/02czkny70","country_code":"CN","type":"education","lineage":["https://openalex.org/I16365422"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhai Yuanjie","raw_affiliation_strings":["Institute of VLSI Design, Hefei University of Technology, Hefei, China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Hefei University of Technology, Hefei, China","institution_ids":["https://openalex.org/I16365422"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5001713932"],"corresponding_institution_ids":["https://openalex.org/I16365422"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.14139919,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"25","issue":null,"first_page":"1775","last_page":"1778"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/observability","display_name":"Observability","score":0.8435788750648499},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8096704483032227},{"id":"https://openalex.org/keywords/property","display_name":"Property (philosophy)","score":0.7142090797424316},{"id":"https://openalex.org/keywords/event","display_name":"Event (particle physics)","score":0.6899946928024292},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.6139978170394897},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.5926419496536255},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.5888053178787231},{"id":"https://openalex.org/keywords/automaton","display_name":"Automaton","score":0.5323622226715088},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.5138654708862305},{"id":"https://openalex.org/keywords/sequence","display_name":"Sequence (biology)","score":0.49556100368499756},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.47799602150917053},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.4776693284511566},{"id":"https://openalex.org/keywords/formal-methods","display_name":"Formal methods","score":0.4658551812171936},{"id":"https://openalex.org/keywords/formal-specification","display_name":"Formal specification","score":0.4545518457889557},{"id":"https://openalex.org/keywords/temporal-logic","display_name":"Temporal logic","score":0.4148717522621155},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.4037080407142639},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3810000419616699},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3611290752887726},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08925950527191162}],"concepts":[{"id":"https://openalex.org/C36299963","wikidata":"https://www.wikidata.org/wiki/Q1369844","display_name":"Observability","level":2,"score":0.8435788750648499},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8096704483032227},{"id":"https://openalex.org/C189950617","wikidata":"https://www.wikidata.org/wiki/Q937228","display_name":"Property (philosophy)","level":2,"score":0.7142090797424316},{"id":"https://openalex.org/C2779662365","wikidata":"https://www.wikidata.org/wiki/Q5416694","display_name":"Event (particle physics)","level":2,"score":0.6899946928024292},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.6139978170394897},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.5926419496536255},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.5888053178787231},{"id":"https://openalex.org/C112505250","wikidata":"https://www.wikidata.org/wiki/Q787116","display_name":"Automaton","level":2,"score":0.5323622226715088},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.5138654708862305},{"id":"https://openalex.org/C2778112365","wikidata":"https://www.wikidata.org/wiki/Q3511065","display_name":"Sequence (biology)","level":2,"score":0.49556100368499756},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.47799602150917053},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.4776693284511566},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.4658551812171936},{"id":"https://openalex.org/C116253237","wikidata":"https://www.wikidata.org/wiki/Q1437424","display_name":"Formal specification","level":2,"score":0.4545518457889557},{"id":"https://openalex.org/C25016198","wikidata":"https://www.wikidata.org/wiki/Q781833","display_name":"Temporal logic","level":2,"score":0.4148717522621155},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.4037080407142639},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3810000419616699},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3611290752887726},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08925950527191162},{"id":"https://openalex.org/C28826006","wikidata":"https://www.wikidata.org/wiki/Q33521","display_name":"Applied mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2008.4746385","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2008.4746385","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2011645538","https://openalex.org/W2110852937","https://openalex.org/W2112134383","https://openalex.org/W2118970405","https://openalex.org/W2150764159","https://openalex.org/W2165566357"],"related_works":["https://openalex.org/W2049993111","https://openalex.org/W1903167137","https://openalex.org/W2145025660","https://openalex.org/W2171674700","https://openalex.org/W1922520186","https://openalex.org/W1544097700","https://openalex.org/W1946493810","https://openalex.org/W1495250406","https://openalex.org/W17088386","https://openalex.org/W1608485412"],"abstract_inverted_index":{"Aiming":[0],"at":[1],"the":[2,26,29,40,47,58,85,89,98,121,131,137,152],"requirements":[3,27],"of":[4,10,28,91,97,123,128],"real-time":[5],"ability":[6],"and":[7,103,130,151],"good":[8],"observability":[9],"result-checking":[11],"in":[12,115,140],"IC":[13],"functional":[14],"verification,":[15],"a":[16,35,67],"method":[17,90,138],"was":[18,37,107,113],"proposed":[19,139],"to":[20,32,49,119,154],"generate":[21],"monitors":[22,61,80],"automatically.":[23],"Based":[24,56],"on":[25,57,84],"design":[30,148],"property":[31,149],"be":[33,50,53,63,155],"monitored,":[34],"sub-set":[36],"defined":[38],"from":[39],"Property":[41],"Specification":[42],"Language":[43],"(PSL),":[44],"so":[45],"that":[46,136],"objects":[48],"monitored":[51],"can":[52,62],"formally":[54],"described.":[55],"formal":[59,71],"descriptions,":[60],"generated":[64,82],"automatically":[65],"through":[66,88],"two-step":[68],"method.":[69,125],"The":[70,126],"descriptions":[72],"are":[73,81],"transferred":[74],"into":[75],"event":[76,86,101],"sequences":[77,87],"first.":[78],"Then":[79],"based":[83,133],"FSM":[92,104],"automatic":[93],"construction.":[94],"Mathematical":[95],"model":[96],"relationship":[99],"between":[100,146],"sequence":[102],"state":[105],"evolving":[106],"put":[108],"forward.":[109],"Directed":[110],"random":[111],"analysis":[112,129],"applied":[114],"several":[116],"serial":[117],"interfaces":[118],"prove":[120],"effectiveness":[122],"our":[124],"results":[127],"application":[132],"testing":[134],"shows":[135],"this":[141],"paper":[142],"achieves":[143],"better":[144],"tradeoff":[145],"complex":[147],"monitoring":[150],"easiness":[153],"mastered":[156],"by":[157],"verification":[158],"engineers":[159]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
