{"id":"https://openalex.org/W2165376228","doi":"https://doi.org/10.1109/apccas.2008.4746382","title":"A proposed FPGA-based parallel architecture for matrix multiplication","display_name":"A proposed FPGA-based parallel architecture for matrix multiplication","publication_year":2008,"publication_date":"2008-11-01","ids":{"openalex":"https://openalex.org/W2165376228","doi":"https://doi.org/10.1109/apccas.2008.4746382","mag":"2165376228"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2008.4746382","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2008.4746382","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5045666717","display_name":"Syed Manzoor Qasim","orcid":"https://orcid.org/0000-0002-6407-2092"},"institutions":[{"id":"https://openalex.org/I28022161","display_name":"King Saud University","ror":"https://ror.org/02f81g417","country_code":"SA","type":"education","lineage":["https://openalex.org/I28022161"]}],"countries":["SA"],"is_corresponding":true,"raw_author_name":"Syed Manzoor Qasim","raw_affiliation_strings":["Department of Electrical Engineering, Saud University College of Engineering, Riyadh, Saudi Arabia"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Saud University College of Engineering, Riyadh, Saudi Arabia","institution_ids":["https://openalex.org/I28022161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084067631","display_name":"Shuja A. Abbasi","orcid":null},"institutions":[{"id":"https://openalex.org/I28022161","display_name":"King Saud University","ror":"https://ror.org/02f81g417","country_code":"SA","type":"education","lineage":["https://openalex.org/I28022161"]}],"countries":["SA"],"is_corresponding":false,"raw_author_name":"Shuja Ahmad Abbasi","raw_affiliation_strings":["Department of Electrical Engineering, Saud University College of Engineering, Riyadh, Saudi Arabia"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Saud University College of Engineering, Riyadh, Saudi Arabia","institution_ids":["https://openalex.org/I28022161"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112226177","display_name":"B. Almashary","orcid":null},"institutions":[{"id":"https://openalex.org/I28022161","display_name":"King Saud University","ror":"https://ror.org/02f81g417","country_code":"SA","type":"education","lineage":["https://openalex.org/I28022161"]}],"countries":["SA"],"is_corresponding":false,"raw_author_name":"Bandar Almashary","raw_affiliation_strings":["Department of Electrical Engineering, Saud University College of Engineering, Riyadh, Saudi Arabia"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Saud University College of Engineering, Riyadh, Saudi Arabia","institution_ids":["https://openalex.org/I28022161"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5045666717"],"corresponding_institution_ids":["https://openalex.org/I28022161"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.13540044,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1763","last_page":"1766"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8808612823486328},{"id":"https://openalex.org/keywords/multiplication","display_name":"Multiplication (music)","score":0.7802433371543884},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7447415590286255},{"id":"https://openalex.org/keywords/matrix-multiplication","display_name":"Matrix multiplication","score":0.675226092338562},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6186285614967346},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5246553421020508},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5107681751251221},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4666310250759125},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.42746439576148987},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3455323576927185},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32632219791412354},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09632566571235657},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.06394737958908081}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8808612823486328},{"id":"https://openalex.org/C2780595030","wikidata":"https://www.wikidata.org/wiki/Q3860309","display_name":"Multiplication (music)","level":2,"score":0.7802433371543884},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7447415590286255},{"id":"https://openalex.org/C17349429","wikidata":"https://www.wikidata.org/wiki/Q1049914","display_name":"Matrix multiplication","level":3,"score":0.675226092338562},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6186285614967346},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5246553421020508},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5107681751251221},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4666310250759125},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.42746439576148987},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3455323576927185},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32632219791412354},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09632566571235657},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.06394737958908081},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C84114770","wikidata":"https://www.wikidata.org/wiki/Q46344","display_name":"Quantum","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2008.4746382","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2008.4746382","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5299999713897705,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1511216606","https://openalex.org/W1545917641","https://openalex.org/W1791017232","https://openalex.org/W1820726733","https://openalex.org/W1833016444","https://openalex.org/W1925692259","https://openalex.org/W1969644170","https://openalex.org/W1986466110","https://openalex.org/W2043990632","https://openalex.org/W2100966314","https://openalex.org/W2107356030","https://openalex.org/W2111905534","https://openalex.org/W2163916557","https://openalex.org/W2164468054","https://openalex.org/W2170510975","https://openalex.org/W2506157605","https://openalex.org/W4246843485","https://openalex.org/W6630990198","https://openalex.org/W6638433071","https://openalex.org/W6642831272"],"related_works":["https://openalex.org/W3099313426","https://openalex.org/W4287593139","https://openalex.org/W752783541","https://openalex.org/W1506547947","https://openalex.org/W2995605830","https://openalex.org/W4206811032","https://openalex.org/W4399458808","https://openalex.org/W2086123442","https://openalex.org/W1967938402","https://openalex.org/W2596457687"],"abstract_inverted_index":{"Matrix":[0],"multiplication":[1,37],"is":[2],"a":[3,32],"computation":[4],"intensive":[5],"operation":[6,23],"and":[7,15,54,77],"plays":[8],"an":[9],"important":[10],"role":[11],"in":[12,27],"many":[13],"scientific":[14],"engineering":[16],"applications.":[17],"For":[18],"high":[19],"performance":[20,65],"applications,":[21],"this":[22],"must":[24],"be":[25],"realized":[26],"hardware.":[28],"This":[29],"paper":[30],"presents":[31],"parallel":[33],"architecture":[34,49],"for":[35],"the":[36],"of":[38,58],"two":[39],"matrices":[40],"using":[41],"field":[42],"programmable":[43],"gate":[44],"array":[45],"(FPGA).":[46],"The":[47],"proposed":[48],"employs":[50],"advanced":[51],"design":[52],"techniques":[53],"exploits":[55],"architectural":[56],"features":[57],"FPGA.":[59],"Results":[60],"show":[61],"that":[62],"it":[63],"provides":[64],"improvements":[66],"over":[67],"previously":[68],"reported":[69],"hardware":[70],"implementation.":[71],"FPGA":[72],"implementation":[73],"results":[74],"are":[75],"presented":[76],"discussed.":[78]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2012,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}