{"id":"https://openalex.org/W2135415916","doi":"https://doi.org/10.1109/apccas.2008.4746218","title":"Robust solution for synchronous communication among multi clock domains","display_name":"Robust solution for synchronous communication among multi clock domains","publication_year":2008,"publication_date":"2008-11-01","ids":{"openalex":"https://openalex.org/W2135415916","doi":"https://doi.org/10.1109/apccas.2008.4746218","mag":"2135415916"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2008.4746218","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2008.4746218","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018531470","display_name":"J. Semi\u00e3o","orcid":"https://orcid.org/0000-0002-7667-7910"},"institutions":[{"id":"https://openalex.org/I71503853","display_name":"University of Algarve","ror":"https://ror.org/014g34x36","country_code":"PT","type":"education","lineage":["https://openalex.org/I71503853"]}],"countries":["PT"],"is_corresponding":true,"raw_author_name":"J. Semiao","raw_affiliation_strings":["School of Technology, University of Algarve, Faro, Portugal","Sch. of Technol., Univ. of Algarve, Faro"],"affiliations":[{"raw_affiliation_string":"School of Technology, University of Algarve, Faro, Portugal","institution_ids":["https://openalex.org/I71503853"]},{"raw_affiliation_string":"Sch. of Technol., Univ. of Algarve, Faro","institution_ids":["https://openalex.org/I71503853"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100654417","display_name":"J. Varela","orcid":"https://orcid.org/0000-0003-2613-3146"},"institutions":[{"id":"https://openalex.org/I67311998","display_name":"European Organization for Nuclear Research","ror":"https://ror.org/01ggx4157","country_code":"CH","type":"facility","lineage":["https://openalex.org/I67311998"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"J. Varela","raw_affiliation_strings":["CERN, Geneva, Switzerland","CERN, Geneve"],"affiliations":[{"raw_affiliation_string":"CERN, Geneva, Switzerland","institution_ids":["https://openalex.org/I67311998"]},{"raw_affiliation_string":"CERN, Geneve","institution_ids":["https://openalex.org/I67311998"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014518141","display_name":"J. Freijedo","orcid":"https://orcid.org/0000-0002-5462-173X"},"institutions":[{"id":"https://openalex.org/I6289922","display_name":"Universidade de Vigo","ror":"https://ror.org/05rdf8595","country_code":"ES","type":"education","lineage":["https://openalex.org/I6289922"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J. Freijedo","raw_affiliation_strings":["Department of Electronic Technology, University of Vigo, Vigo, Spain","Dep. of Electron. Technol., Univ. of Vigo, Vigo"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Technology, University of Vigo, Vigo, Spain","institution_ids":["https://openalex.org/I6289922"]},{"raw_affiliation_string":"Dep. of Electron. Technol., Univ. of Vigo, Vigo","institution_ids":["https://openalex.org/I6289922"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057597956","display_name":"Juan J. Rodr\u00edguez-Andina","orcid":"https://orcid.org/0000-0002-0919-1793"},"institutions":[{"id":"https://openalex.org/I6289922","display_name":"Universidade de Vigo","ror":"https://ror.org/05rdf8595","country_code":"ES","type":"education","lineage":["https://openalex.org/I6289922"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J. Andina","raw_affiliation_strings":["Department of Electronic Technology, University of Vigo, Vigo, Spain","Dep. of Electron. Technol., Univ. of Vigo, Vigo"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Technology, University of Vigo, Vigo, Spain","institution_ids":["https://openalex.org/I6289922"]},{"raw_affiliation_string":"Dep. of Electron. Technol., Univ. of Vigo, Vigo","institution_ids":["https://openalex.org/I6289922"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112805367","display_name":"C. Leong","orcid":"https://orcid.org/0000-0001-6132-3741"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"C. Leong","raw_affiliation_strings":["IST/INESC, Lisboa, Portugal","IST / INESC-ID Lisbon, Lisbon"],"affiliations":[{"raw_affiliation_string":"IST/INESC, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201"]},{"raw_affiliation_string":"IST / INESC-ID Lisbon, Lisbon","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058862498","display_name":"J.P. Teixeira","orcid":"https://orcid.org/0000-0002-0379-6257"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"J.P. Teixeira","raw_affiliation_strings":["IST/INESC, Lisboa, Portugal","IST / INESC-ID Lisbon, Lisbon"],"affiliations":[{"raw_affiliation_string":"IST/INESC, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201"]},{"raw_affiliation_string":"IST / INESC-ID Lisbon, Lisbon","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039557784","display_name":"I.C. Teixeira","orcid":"https://orcid.org/0000-0002-2642-5619"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"I. Teixeira","raw_affiliation_strings":["IST/INESC, Lisboa, Portugal","IST / INESC-ID Lisbon, Lisbon"],"affiliations":[{"raw_affiliation_string":"IST/INESC, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201"]},{"raw_affiliation_string":"IST / INESC-ID Lisbon, Lisbon","institution_ids":["https://openalex.org/I121345201"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5018531470"],"corresponding_institution_ids":["https://openalex.org/I71503853"],"apc_list":null,"apc_paid":null,"fwci":0.7332,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.77060989,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1107","last_page":"1110"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.902177631855011},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.827314019203186},{"id":"https://openalex.org/keywords/dependability","display_name":"Dependability","score":0.8162499666213989},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7895199060440063},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6218869686126709},{"id":"https://openalex.org/keywords/communications-system","display_name":"Communications system","score":0.5600141286849976},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.500338077545166},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.48599323630332947},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.44414186477661133},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43560516834259033},{"id":"https://openalex.org/keywords/data-transmission","display_name":"Data transmission","score":0.42564719915390015},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2145858108997345},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.17810189723968506},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.13799816370010376},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0899730920791626}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.902177631855011},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.827314019203186},{"id":"https://openalex.org/C77019957","wikidata":"https://www.wikidata.org/wiki/Q2689057","display_name":"Dependability","level":2,"score":0.8162499666213989},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7895199060440063},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6218869686126709},{"id":"https://openalex.org/C101765175","wikidata":"https://www.wikidata.org/wiki/Q577764","display_name":"Communications system","level":2,"score":0.5600141286849976},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.500338077545166},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.48599323630332947},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.44414186477661133},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43560516834259033},{"id":"https://openalex.org/C557945733","wikidata":"https://www.wikidata.org/wiki/Q389772","display_name":"Data transmission","level":2,"score":0.42564719915390015},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2145858108997345},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.17810189723968506},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.13799816370010376},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0899730920791626},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2008.4746218","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2008.4746218","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W107946387","https://openalex.org/W114110321","https://openalex.org/W1963638851","https://openalex.org/W2004171361","https://openalex.org/W2052329921","https://openalex.org/W2068293704","https://openalex.org/W2081119285","https://openalex.org/W2104610013","https://openalex.org/W2117897741","https://openalex.org/W2146365466","https://openalex.org/W2147602339","https://openalex.org/W2156802302","https://openalex.org/W4234063696","https://openalex.org/W4235889727","https://openalex.org/W4285719527","https://openalex.org/W6604444894"],"related_works":["https://openalex.org/W4386292891","https://openalex.org/W4232628459","https://openalex.org/W4386968318","https://openalex.org/W2147289961","https://openalex.org/W2052455055","https://openalex.org/W2144402314","https://openalex.org/W2384756109","https://openalex.org/W2147595938","https://openalex.org/W364924225","https://openalex.org/W142020038"],"abstract_inverted_index":{"The":[0,120],"purpose":[1],"of":[2,77,84,92,122],"this":[3,70],"paper":[4,71],"is":[5,30,125],"to":[6,74,100,112],"present":[7],"a":[8,16,128],"new":[9],"robust":[10,23],"methodology":[11,124],"for":[12,44,59],"synchronous":[13,53,93],"communications":[14,54],"in":[15,127],"BUS,":[17],"connecting":[18],"multi-clock":[19],"domains.":[20],"Traditionally,":[21],"when":[22,63],"solutions":[24,40],"are":[25,67,136],"needed,":[26],"an":[27],"asynchronous":[28,39,85],"communication":[29,86,104],"used.":[31],"However,":[32],"the":[33,50,82,88,102,118,123],"low":[34],"transfer":[35],"rates":[36],"associated":[37],"with":[38],"make":[41],"them":[42],"inadequate":[43],"high":[45],"performance":[46],"digital":[47],"systems.":[48],"On":[49],"other":[51],"hand,":[52],"do":[55],"not":[56],"guarantee":[57],"dependability":[58],"all":[60],"data,":[61],"especially":[62],"different":[64],"clock":[65],"domains":[66],"interconnected.":[68],"In":[69],"we":[72],"propose":[73],"take":[75],"advantage":[76],"these":[78],"approaches,":[79],"by":[80],"combining,":[81],"robustness":[83],"and":[87,90,116],"speed":[89],"simplicity":[91],"communications.":[94],"A":[95,106],"structure":[96,115],"has":[97,109],"been":[98,110],"developed":[99],"implement":[101,113],"proposed":[103],"approach.":[105],"test":[107],"chip":[108],"designed":[111],"that":[114],"prove":[117],"concept.":[119],"usefulness":[121],"demonstrated":[126],"complex":[129],"FPGA":[130],"data":[131],"acquisition":[132],"system.":[133],"Simulation":[134],"results":[135],"presented.":[137]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
