{"id":"https://openalex.org/W2113073462","doi":"https://doi.org/10.1109/apccas.2008.4746195","title":"A second-order gate delay modeling method with an efficient sensitivity analysis","display_name":"A second-order gate delay modeling method with an efficient sensitivity analysis","publication_year":2008,"publication_date":"2008-11-01","ids":{"openalex":"https://openalex.org/W2113073462","doi":"https://doi.org/10.1109/apccas.2008.4746195","mag":"2113073462"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2008.4746195","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2008.4746195","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090206630","display_name":"Sangwoo Han","orcid":"https://orcid.org/0000-0002-3729-7405"},"institutions":[{"id":"https://openalex.org/I148751991","display_name":"Sogang University","ror":"https://ror.org/056tn4839","country_code":"KR","type":"education","lineage":["https://openalex.org/I148751991"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Sangwoo Han","raw_affiliation_strings":["Department of Computer Science and Engineering, Sogang University, Seoul, South Korea","Dept. of Comput. Sci. & Eng., Sogang Univ., Seoul"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Sogang University, Seoul, South Korea","institution_ids":["https://openalex.org/I148751991"]},{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., Sogang Univ., Seoul","institution_ids":["https://openalex.org/I148751991"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044191111","display_name":"Yooseong Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I148751991","display_name":"Sogang University","ror":"https://ror.org/056tn4839","country_code":"KR","type":"education","lineage":["https://openalex.org/I148751991"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Yooseong Kim","raw_affiliation_strings":["Department of Computer Science and Engineering, Sogang University, Seoul, South Korea","Dept. of Comput. Sci. & Eng., Sogang Univ., Seoul"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Sogang University, Seoul, South Korea","institution_ids":["https://openalex.org/I148751991"]},{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., Sogang Univ., Seoul","institution_ids":["https://openalex.org/I148751991"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083042041","display_name":"Woosick Choi","orcid":null},"institutions":[{"id":"https://openalex.org/I10654025","display_name":"SK Group (United States)","ror":"https://ror.org/00qajw440","country_code":"US","type":"company","lineage":["https://openalex.org/I10654025","https://openalex.org/I134353371"]},{"id":"https://openalex.org/I134353371","display_name":"SK Group (South Korea)","ror":"https://ror.org/03696td91","country_code":"KR","type":"company","lineage":["https://openalex.org/I134353371"]}],"countries":["KR","US"],"is_corresponding":false,"raw_author_name":"Woosick Choi","raw_affiliation_strings":["Design Automation Team of Computer Aided Engineering, Hynix Semiconductor, Inc., Icheon, South Korea","Design Autom. Team of Comput. Aided Eng., Hynix Semicond., Inc., Icheon"],"affiliations":[{"raw_affiliation_string":"Design Automation Team of Computer Aided Engineering, Hynix Semiconductor, Inc., Icheon, South Korea","institution_ids":["https://openalex.org/I134353371"]},{"raw_affiliation_string":"Design Autom. Team of Comput. Aided Eng., Hynix Semicond., Inc., Icheon","institution_ids":["https://openalex.org/I10654025"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112980644","display_name":"Inho Shin","orcid":null},"institutions":[{"id":"https://openalex.org/I134353371","display_name":"SK Group (South Korea)","ror":"https://ror.org/03696td91","country_code":"KR","type":"company","lineage":["https://openalex.org/I134353371"]},{"id":"https://openalex.org/I10654025","display_name":"SK Group (United States)","ror":"https://ror.org/00qajw440","country_code":"US","type":"company","lineage":["https://openalex.org/I10654025","https://openalex.org/I134353371"]}],"countries":["KR","US"],"is_corresponding":false,"raw_author_name":"Inho Shin","raw_affiliation_strings":["Design Automation Team of Computer Aided Engineering, Hynix Semiconductor, Inc., Icheon, South Korea","Design Autom. Team of Comput. Aided Eng., Hynix Semicond., Inc., Icheon"],"affiliations":[{"raw_affiliation_string":"Design Automation Team of Computer Aided Engineering, Hynix Semiconductor, Inc., Icheon, South Korea","institution_ids":["https://openalex.org/I134353371"]},{"raw_affiliation_string":"Design Autom. Team of Comput. Aided Eng., Hynix Semicond., Inc., Icheon","institution_ids":["https://openalex.org/I10654025"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5086796585","display_name":"Youngdoo Choi","orcid":"https://orcid.org/0000-0003-3501-3058"},"institutions":[{"id":"https://openalex.org/I10654025","display_name":"SK Group (United States)","ror":"https://ror.org/00qajw440","country_code":"US","type":"company","lineage":["https://openalex.org/I10654025","https://openalex.org/I134353371"]},{"id":"https://openalex.org/I134353371","display_name":"SK Group (South Korea)","ror":"https://ror.org/03696td91","country_code":"KR","type":"company","lineage":["https://openalex.org/I134353371"]}],"countries":["KR","US"],"is_corresponding":false,"raw_author_name":"Youngdoo Choi","raw_affiliation_strings":["Design Automation Team of Computer Aided Engineering, Hynix Semiconductor, Inc., Icheon, South Korea","Design Autom. Team of Comput. Aided Eng., Hynix Semicond., Inc., Icheon"],"affiliations":[{"raw_affiliation_string":"Design Automation Team of Computer Aided Engineering, Hynix Semiconductor, Inc., Icheon, South Korea","institution_ids":["https://openalex.org/I134353371"]},{"raw_affiliation_string":"Design Autom. Team of Comput. Aided Eng., Hynix Semicond., Inc., Icheon","institution_ids":["https://openalex.org/I10654025"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5090206630"],"corresponding_institution_ids":["https://openalex.org/I148751991"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.13355376,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1008","last_page":"1011"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sensitivity","display_name":"Sensitivity (control systems)","score":0.719588041305542},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.5831651091575623},{"id":"https://openalex.org/keywords/standard-deviation","display_name":"Standard deviation","score":0.5228398442268372},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.5172634720802307},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.5096688270568848},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.49569451808929443},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4927401840686798},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.48708510398864746},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4679276943206787},{"id":"https://openalex.org/keywords/variance","display_name":"Variance (accounting)","score":0.467647522687912},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.43715134263038635},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.42677342891693115},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3554217517375946},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.30605369806289673},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2414465844631195},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1883845031261444},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.17379197478294373},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11058631539344788}],"concepts":[{"id":"https://openalex.org/C21200559","wikidata":"https://www.wikidata.org/wiki/Q7451068","display_name":"Sensitivity (control systems)","level":2,"score":0.719588041305542},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.5831651091575623},{"id":"https://openalex.org/C22679943","wikidata":"https://www.wikidata.org/wiki/Q159375","display_name":"Standard deviation","level":2,"score":0.5228398442268372},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.5172634720802307},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.5096688270568848},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.49569451808929443},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4927401840686798},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.48708510398864746},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4679276943206787},{"id":"https://openalex.org/C196083921","wikidata":"https://www.wikidata.org/wiki/Q7915758","display_name":"Variance (accounting)","level":2,"score":0.467647522687912},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.43715134263038635},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.42677342891693115},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3554217517375946},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.30605369806289673},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2414465844631195},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1883845031261444},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.17379197478294373},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11058631539344788},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C121955636","wikidata":"https://www.wikidata.org/wiki/Q4116214","display_name":"Accounting","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2008.4746195","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2008.4746195","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1966741973","https://openalex.org/W2000836282","https://openalex.org/W2055180707","https://openalex.org/W2104785869","https://openalex.org/W2105638176","https://openalex.org/W2120116751","https://openalex.org/W2138451337","https://openalex.org/W2144242878","https://openalex.org/W2168908441","https://openalex.org/W2169340912","https://openalex.org/W2172291058","https://openalex.org/W4233746278","https://openalex.org/W4240264115","https://openalex.org/W4254506919"],"related_works":["https://openalex.org/W2367891013","https://openalex.org/W2007108787","https://openalex.org/W4252337044","https://openalex.org/W2084837496","https://openalex.org/W118630527","https://openalex.org/W2103570580","https://openalex.org/W2444511150","https://openalex.org/W1804063983","https://openalex.org/W2134944363","https://openalex.org/W2057470132"],"abstract_inverted_index":{"As":[0],"CMOS":[1],"technology":[2],"scales,":[3],"to":[4,19,67,77,100,134],"consider":[5],"process":[6,24,76],"variation":[7,25],"becomes":[8],"increasingly":[9],"challenging.":[10],"Statistical":[11],"gate":[12,27,33],"delay":[13,34],"model":[14,35,87,113],"is":[15,37,56,71,88,143],"widely":[16],"used":[17],"technique":[18],"analyze":[20],"the":[21,42,75,86,104,111,125,130,135],"influence":[22],"of":[23,45,49,85,118,129],"on":[26,92],"delay.":[28],"We":[29,123],"propose":[30],"a":[31,93,97],"second-order":[32,54],"which":[36],"more":[38],"accurate":[39],"even":[40],"with":[41],"larger":[43],"variance":[44],"variations.":[46],"The":[47,64,83,138],"number":[48],"additional":[50],"variables":[51],"introduced":[52],"by":[53,73,90,110],"terms":[55],"minimized":[57],"using":[58],"sensitivities":[59],"and":[60,80,96,106,120],"statistically":[61],"combined":[62],"variables.":[63],"runtime":[65],"cost":[66],"calculate":[68],"sensitivity":[69],"values":[70],"reduced":[72],"simplifying":[74],"determine":[78],"worst-case":[79],"best-case":[81],"parameters.":[82],"accuracy":[84],"verified":[89],"experiments":[91],"gate,":[94],"inverter-chain,":[95],"circuit.":[98],"Comparing":[99],"Monte":[101],"Carlo":[102],"simulation,":[103],"mean":[105],"standard":[107],"deviation":[108],"obtained":[109],"proposed":[112,131],"have":[114],"average":[115,139],"error":[116,126,140],"rates":[117],"1.26%":[119],"4.31%,":[121],"respectively.":[122],"present":[124],"reduction":[127,141],"rate":[128,142],"model,":[132],"compared":[133],"first-order":[136],"model.":[137],"36.7%.":[144]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}