{"id":"https://openalex.org/W2060497355","doi":"https://doi.org/10.1109/apccas.2008.4746193","title":"Timing driven force-directed floorplanning with incremental static timing analyzer","display_name":"Timing driven force-directed floorplanning with incremental static timing analyzer","publication_year":2008,"publication_date":"2008-11-01","ids":{"openalex":"https://openalex.org/W2060497355","doi":"https://doi.org/10.1109/apccas.2008.4746193","mag":"2060497355"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2008.4746193","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2008.4746193","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071396425","display_name":"Won-Jin Kim","orcid":"https://orcid.org/0000-0003-2473-815X"},"institutions":[{"id":"https://openalex.org/I4575257","display_name":"Hanyang University","ror":"https://ror.org/046865y68","country_code":"KR","type":"education","lineage":["https://openalex.org/I4575257"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Won-Jin Kim","raw_affiliation_strings":["Dept. of Electronics, Computer and Communication Engineering, Hanyang University, Seoul, Korea","Dept. of Electron. Comput. & Commun. Eng., Hanyang Univ., Seoul"],"affiliations":[{"raw_affiliation_string":"Dept. of Electronics, Computer and Communication Engineering, Hanyang University, Seoul, Korea","institution_ids":["https://openalex.org/I4575257"]},{"raw_affiliation_string":"Dept. of Electron. Comput. & Commun. Eng., Hanyang Univ., Seoul","institution_ids":["https://openalex.org/I4575257"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031594156","display_name":"Byung-Gyu Ahn","orcid":null},"institutions":[{"id":"https://openalex.org/I4575257","display_name":"Hanyang University","ror":"https://ror.org/046865y68","country_code":"KR","type":"education","lineage":["https://openalex.org/I4575257"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Byung-Gyu Ahn","raw_affiliation_strings":["Dept. of Electronics, Computer and Communication Engineering, Hanyang University, Seoul, Korea","Dept. of Electron. Comput. & Commun. Eng., Hanyang Univ., Seoul"],"affiliations":[{"raw_affiliation_string":"Dept. of Electronics, Computer and Communication Engineering, Hanyang University, Seoul, Korea","institution_ids":["https://openalex.org/I4575257"]},{"raw_affiliation_string":"Dept. of Electron. Comput. & Commun. Eng., Hanyang Univ., Seoul","institution_ids":["https://openalex.org/I4575257"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090391516","display_name":"Ki\u2010Seok Chung","orcid":"https://orcid.org/0000-0002-2908-8443"},"institutions":[{"id":"https://openalex.org/I4575257","display_name":"Hanyang University","ror":"https://ror.org/046865y68","country_code":"KR","type":"education","lineage":["https://openalex.org/I4575257"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Ki-Seok Chung","raw_affiliation_strings":["Dept. of Electronics, Computer and Communication Engineering, Hanyang University, Seoul, Korea","Dept. of Electron. Comput. & Commun. Eng., Hanyang Univ., Seoul"],"affiliations":[{"raw_affiliation_string":"Dept. of Electronics, Computer and Communication Engineering, Hanyang University, Seoul, Korea","institution_ids":["https://openalex.org/I4575257"]},{"raw_affiliation_string":"Dept. of Electron. Comput. & Commun. Eng., Hanyang Univ., Seoul","institution_ids":["https://openalex.org/I4575257"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111781066","display_name":"Jong-Wha Chung","orcid":null},"institutions":[{"id":"https://openalex.org/I4575257","display_name":"Hanyang University","ror":"https://ror.org/046865y68","country_code":"KR","type":"education","lineage":["https://openalex.org/I4575257"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jong-Wha Chung","raw_affiliation_strings":["Hanyang University, Seongdong-gu, Seoul, KR","Dept. of Electron. Comput. & Commun. Eng., Hanyang Univ., Seoul"],"affiliations":[{"raw_affiliation_string":"Hanyang University, Seongdong-gu, Seoul, KR","institution_ids":["https://openalex.org/I4575257"]},{"raw_affiliation_string":"Dept. of Electron. Comput. & Commun. Eng., Hanyang Univ., Seoul","institution_ids":["https://openalex.org/I4575257"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111781067","display_name":"Sung-Hwan Oh","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Sung-Hwan Oh","raw_affiliation_strings":["Entasys Design Inc., Seoul, Korea","Entasys Design Inc., Seoul"],"affiliations":[{"raw_affiliation_string":"Entasys Design Inc., Seoul, Korea","institution_ids":[]},{"raw_affiliation_string":"Entasys Design Inc., Seoul","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5071396425"],"corresponding_institution_ids":["https://openalex.org/I4575257"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.10157648,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1000","last_page":"1003"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9954000115394592,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9875576496124268},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7547734379768372},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7010990977287292},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.6713457703590393},{"id":"https://openalex.org/keywords/estimator","display_name":"Estimator","score":0.5159100294113159},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4745522141456604},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.42117932438850403},{"id":"https://openalex.org/keywords/spectrum-analyzer","display_name":"Spectrum analyzer","score":0.4195970892906189},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4107059836387634},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.4102151095867157},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.32439589500427246},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.27115899324417114},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20296230912208557},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.1966903805732727},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.13866031169891357},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08046308159828186},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06244352459907532}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9875576496124268},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7547734379768372},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7010990977287292},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.6713457703590393},{"id":"https://openalex.org/C185429906","wikidata":"https://www.wikidata.org/wiki/Q1130160","display_name":"Estimator","level":2,"score":0.5159100294113159},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4745522141456604},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.42117932438850403},{"id":"https://openalex.org/C158007255","wikidata":"https://www.wikidata.org/wiki/Q1055222","display_name":"Spectrum analyzer","level":2,"score":0.4195970892906189},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4107059836387634},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.4102151095867157},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.32439589500427246},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.27115899324417114},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20296230912208557},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.1966903805732727},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.13866031169891357},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08046308159828186},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06244352459907532},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2008.4746193","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2008.4746193","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","score":0.6100000143051147,"display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2010988671","https://openalex.org/W2063781085","https://openalex.org/W2097845952","https://openalex.org/W2105925860","https://openalex.org/W2139056947","https://openalex.org/W2162908425"],"related_works":["https://openalex.org/W2903073708","https://openalex.org/W2115502122","https://openalex.org/W2001838379","https://openalex.org/W4211105560","https://openalex.org/W2138401961","https://openalex.org/W1974073956","https://openalex.org/W1525696892","https://openalex.org/W2353155791","https://openalex.org/W2156550631","https://openalex.org/W2030852227"],"abstract_inverted_index":{"As":[0],"nano-scale":[1],"technology":[2],"is":[3,29,75,125],"widely":[4],"adopted,":[5],"minimizing":[6],"the":[7,14,34,113],"interconnection":[8,35,71],"delay":[9,36,72],"has":[10,87],"become":[11],"one":[12],"of":[13,93,115,137],"most":[15],"critical":[16],"issues":[17],"in":[18,127],"designing":[19],"high":[20],"performance":[21],"systems.":[22],"To":[23],"achieve":[24],"fast":[25,68],"timing":[26,50,60,85],"closure,":[27],"it":[28],"very":[30,76],"important":[31,77],"to":[32,78,111],"estimate":[33],"accurately":[37],"at":[38],"an":[39,56,80],"early":[40],"design":[41],"stage.":[42],"In":[43],"this":[44],"paper,":[45],"we":[46],"propose":[47],"a":[48,67,91,94,129,134],"novel":[49],"driven":[51],"force-directed":[52],"floorplanning":[53,96],"technique":[54],"using":[55],"efficient":[57],"incremental":[58],"static":[59],"analyzer.":[61],"Our":[62],"proposed":[63,84],"floorplan":[64,132],"framework":[65],"contains":[66],"and":[69],"accurate":[70],"estimator":[73],"which":[74],"obtain":[79],"excellent":[81],"floorplan.":[82],"The":[83,118],"methodology":[86],"been":[88],"implemented":[89],"as":[90],"part":[92],"commercial":[95],"tool":[97,124],"called":[98],"Pillar-DP":[99],"from":[100],"Entasys":[101],"Design":[102],"Inc.":[103],"We":[104],"carried":[105],"out":[106],"experiments":[107],"on":[108],"several":[109],"benchmarks":[110],"show":[112,121],"effectiveness":[114],"our":[116,123],"approach.":[117],"experiment":[119],"results":[120],"that":[122],"valuable":[126],"generating":[128],"near":[130],"optimal":[131],"within":[133],"reasonable":[135],"amount":[136],"time.":[138]},"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}