{"id":"https://openalex.org/W2100899581","doi":"https://doi.org/10.1109/apccas.2008.4746184","title":"Single-phase power-gating adiabatic flip-flops","display_name":"Single-phase power-gating adiabatic flip-flops","publication_year":2008,"publication_date":"2008-11-01","ids":{"openalex":"https://openalex.org/W2100899581","doi":"https://doi.org/10.1109/apccas.2008.4746184","mag":"2100899581"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2008.4746184","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2008.4746184","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100339405","display_name":"Hong Li","orcid":"https://orcid.org/0000-0002-6975-7787"},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Hong Li","raw_affiliation_strings":["Faculty of Information Science and Technology, Ningbo University, Ningbo, Zhejiang, China","Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo"],"affiliations":[{"raw_affiliation_string":"Faculty of Information Science and Technology, Ningbo University, Ningbo, Zhejiang, China","institution_ids":["https://openalex.org/I109935558"]},{"raw_affiliation_string":"Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo","institution_ids":["https://openalex.org/I109935558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051536654","display_name":"Lifang Ye","orcid":"https://orcid.org/0000-0002-6748-4690"},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lifang Ye","raw_affiliation_strings":["Faculty of Information Science and Technology, Ningbo University, Ningbo, Zhejiang, China","Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo"],"affiliations":[{"raw_affiliation_string":"Faculty of Information Science and Technology, Ningbo University, Ningbo, Zhejiang, China","institution_ids":["https://openalex.org/I109935558"]},{"raw_affiliation_string":"Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo","institution_ids":["https://openalex.org/I109935558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113744183","display_name":"Jinghong Fu","orcid":null},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinghong Fu","raw_affiliation_strings":["Faculty of Information Science and Technology, Ningbo University, Ningbo, Zhejiang, China","Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo"],"affiliations":[{"raw_affiliation_string":"Faculty of Information Science and Technology, Ningbo University, Ningbo, Zhejiang, China","institution_ids":["https://openalex.org/I109935558"]},{"raw_affiliation_string":"Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo","institution_ids":["https://openalex.org/I109935558"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023402050","display_name":"Jianping Hu","orcid":"https://orcid.org/0000-0002-6469-1061"},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianping Hu","raw_affiliation_strings":["Faculty of Information Science and Technology, Ningbo University, Ningbo, Zhejiang, China","Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo"],"affiliations":[{"raw_affiliation_string":"Faculty of Information Science and Technology, Ningbo University, Ningbo, Zhejiang, China","institution_ids":["https://openalex.org/I109935558"]},{"raw_affiliation_string":"Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo","institution_ids":["https://openalex.org/I109935558"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100339405"],"corresponding_institution_ids":["https://openalex.org/I109935558"],"apc_list":null,"apc_paid":null,"fwci":0.3329,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.6447665,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"9","issue":null,"first_page":"964","last_page":"967"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adiabatic-circuit","display_name":"Adiabatic circuit","score":0.863993763923645},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.8390346765518188},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.7540575265884399},{"id":"https://openalex.org/keywords/adiabatic-process","display_name":"Adiabatic process","score":0.6675835847854614},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.5990573167800903},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.5118059515953064},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.4973762333393097},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4775165617465973},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4751838743686676},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4676736295223236},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4516604542732239},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4227652847766876},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3982153832912445},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3368975520133972},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.27063870429992676},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.26546743512153625},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.20515838265419006},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.1906794309616089},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.18937113881111145},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.15625706315040588},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.12109634280204773},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.10086113214492798},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.09587818384170532}],"concepts":[{"id":"https://openalex.org/C87606752","wikidata":"https://www.wikidata.org/wiki/Q4682637","display_name":"Adiabatic circuit","level":5,"score":0.863993763923645},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.8390346765518188},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.7540575265884399},{"id":"https://openalex.org/C109663097","wikidata":"https://www.wikidata.org/wiki/Q182453","display_name":"Adiabatic process","level":2,"score":0.6675835847854614},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.5990573167800903},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.5118059515953064},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.4973762333393097},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4775165617465973},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4751838743686676},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4676736295223236},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4516604542732239},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4227652847766876},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3982153832912445},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3368975520133972},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27063870429992676},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.26546743512153625},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.20515838265419006},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.1906794309616089},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.18937113881111145},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.15625706315040588},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.12109634280204773},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.10086113214492798},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.09587818384170532},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2008.4746184","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2008.4746184","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8799999952316284}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1833962500","https://openalex.org/W1983067779","https://openalex.org/W2008170349","https://openalex.org/W2015853231","https://openalex.org/W2081041918","https://openalex.org/W2097085895","https://openalex.org/W2119512278","https://openalex.org/W2123607016","https://openalex.org/W2542940887"],"related_works":["https://openalex.org/W2061180121","https://openalex.org/W2546524276","https://openalex.org/W2152979262","https://openalex.org/W4226239708","https://openalex.org/W2100899581","https://openalex.org/W2158114058","https://openalex.org/W2113758237","https://openalex.org/W2188626039","https://openalex.org/W4321463451","https://openalex.org/W2114132980"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"low-power":[3],"power-gating":[4,13,32,35,47,71,86],"adiabatic":[5,14,40,72,87,100,110],"flip-flops":[6,15,73,88],"using":[7],"single-phase":[8,39,53,85,99],"power-clock":[9,54],"scheme.":[10],"The":[11,25,45],"proposed":[12,84],"are":[16,29,49],"realized":[17,81],"with":[18,82],"improved":[19],"CAL":[20],"(Clocked":[21],"Adiabatic":[22],"Logic)":[23],"circuits.":[24],"refresh":[26,66],"enable":[27],"terminals":[28],"added":[30],"for":[31,37],"operation.":[33],"A":[34,77],"scheme":[36],"the":[38,52,67,83,98],"sequential":[41,61,79,101],"circuits":[42,102],"is":[43,89],"described.":[44],"two":[46],"switches":[48],"inserted":[50],"between":[51],"and":[55,64],"virtual":[56],"power-clocks":[57],"to":[58,65],"detach":[59],"power-gated":[60],"logic":[62,111],"blocks":[63,112],"storage":[68],"value":[69],"of":[70,97],"during":[74,113],"idle":[75,114],"periods.":[76,115],"practical":[78],"system":[80],"demonstrated.":[90],"SPICE":[91],"simulations":[92],"show":[93],"that":[94],"energy":[95],"loss":[96],"can":[103],"be":[104],"greatly":[105],"reduced":[106],"by":[107],"shutting":[108],"down":[109]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}