{"id":"https://openalex.org/W2158114058","doi":"https://doi.org/10.1109/apccas.2008.4746155","title":"A power-gating scheme for CAL circuits using single-phase power-clock","display_name":"A power-gating scheme for CAL circuits using single-phase power-clock","publication_year":2008,"publication_date":"2008-11-01","ids":{"openalex":"https://openalex.org/W2158114058","doi":"https://doi.org/10.1109/apccas.2008.4746155","mag":"2158114058"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2008.4746155","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2008.4746155","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100692899","display_name":"Weiqiang Zhang","orcid":"https://orcid.org/0000-0002-0999-4019"},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Weiqiang Zhang","raw_affiliation_strings":["Faculty of Information Science and Technology, Ningbo University, Ningbo, Zhejiang, China"],"affiliations":[{"raw_affiliation_string":"Faculty of Information Science and Technology, Ningbo University, Ningbo, Zhejiang, China","institution_ids":["https://openalex.org/I109935558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055946124","display_name":"Li Su","orcid":null},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Li Su","raw_affiliation_strings":["Faculty of Information Science and Technology, Ningbo University, Ningbo, Zhejiang, China"],"affiliations":[{"raw_affiliation_string":"Faculty of Information Science and Technology, Ningbo University, Ningbo, Zhejiang, China","institution_ids":["https://openalex.org/I109935558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113744183","display_name":"Jinghong Fu","orcid":null},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinghong Fu","raw_affiliation_strings":["Faculty of Information Science and Technology, Ningbo University, Ningbo, Zhejiang, China"],"affiliations":[{"raw_affiliation_string":"Faculty of Information Science and Technology, Ningbo University, Ningbo, Zhejiang, China","institution_ids":["https://openalex.org/I109935558"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109392147","display_name":"Jianping Hu","orcid":null},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianping Hu","raw_affiliation_strings":["Faculty of Information Science and Technology, Ningbo University, Ningbo, Zhejiang, China"],"affiliations":[{"raw_affiliation_string":"Faculty of Information Science and Technology, Ningbo University, Ningbo, Zhejiang, China","institution_ids":["https://openalex.org/I109935558"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100692899"],"corresponding_institution_ids":["https://openalex.org/I109935558"],"apc_list":null,"apc_paid":null,"fwci":1.3318,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.82746481,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"846","last_page":"849"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.865837574005127},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.8398453593254089},{"id":"https://openalex.org/keywords/adiabatic-circuit","display_name":"Adiabatic circuit","score":0.7664614915847778},{"id":"https://openalex.org/keywords/transmission-gate","display_name":"Transmission gate","score":0.6914125084877014},{"id":"https://openalex.org/keywords/idle","display_name":"Idle","score":0.5885409116744995},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.5668663382530212},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5570557117462158},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5563463568687439},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5453751087188721},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5420985221862793},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.500175952911377},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.48307541012763977},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.4583655297756195},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.39183446764945984},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.37693464756011963},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3656122088432312},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2992287874221802},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.29473012685775757},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.2044544816017151},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.17606842517852783},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.15062960982322693},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.0889890193939209}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.865837574005127},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.8398453593254089},{"id":"https://openalex.org/C87606752","wikidata":"https://www.wikidata.org/wiki/Q4682637","display_name":"Adiabatic circuit","level":5,"score":0.7664614915847778},{"id":"https://openalex.org/C2780949067","wikidata":"https://www.wikidata.org/wiki/Q1136752","display_name":"Transmission gate","level":4,"score":0.6914125084877014},{"id":"https://openalex.org/C16320812","wikidata":"https://www.wikidata.org/wiki/Q1812200","display_name":"Idle","level":2,"score":0.5885409116744995},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.5668663382530212},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5570557117462158},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5563463568687439},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5453751087188721},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5420985221862793},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.500175952911377},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.48307541012763977},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.4583655297756195},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.39183446764945984},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.37693464756011963},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3656122088432312},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2992287874221802},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.29473012685775757},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.2044544816017151},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.17606842517852783},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.15062960982322693},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0889890193939209},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2008.4746155","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2008.4746155","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.9100000262260437,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1535100460","https://openalex.org/W1833962500","https://openalex.org/W2008170349","https://openalex.org/W2015853231","https://openalex.org/W2097085895","https://openalex.org/W2119512278","https://openalex.org/W2122984966","https://openalex.org/W2123607016","https://openalex.org/W2155641317","https://openalex.org/W2542940887","https://openalex.org/W3103339143"],"related_works":["https://openalex.org/W2100899581","https://openalex.org/W2548567058","https://openalex.org/W2158114058","https://openalex.org/W2113758237","https://openalex.org/W3195716372","https://openalex.org/W2898743978","https://openalex.org/W2188626039","https://openalex.org/W1535100460","https://openalex.org/W4366088550","https://openalex.org/W2090602390"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3],"power-gating":[4,26,62],"scheme":[5],"for":[6],"CAL":[7,41,54],"(Clocked":[8],"Adiabatic":[9],"Logic)":[10],"circuits":[11,55,65],"to":[12,38,58],"reduce":[13],"energy":[14],"loss":[15,78],"during":[16,44],"idle":[17,45,86],"state.":[18],"A":[19],"transmission":[20],"gate":[21],"is":[22,29],"used":[23,57],"as":[24],"the":[25,32,53,60,69],"switch.":[27],"It":[28],"inserted":[30],"between":[31],"single-phase":[33],"power-clock":[34],"and":[35],"virtual":[36],"power-clocks":[37],"detach":[39],"power-gated":[40],"logic":[42,88],"blocks":[43],"periods.":[46],"The":[47],"8-bit":[48],"full":[49],"adders":[50],"based":[51],"on":[52],"are":[56,66],"verify":[59],"proposed":[61],"technique.":[63],"All":[64],"simulated":[67],"using":[68],"BSIM3V3":[70],"models":[71],"of":[72],"TSMC":[73],"0.18\u03bcm":[74],"CMOS":[75],"technology.":[76],"Energy":[77],"can":[79],"be":[80],"reduced":[81],"greatly":[82],"by":[83],"shutting":[84],"down":[85],"adiabatic":[87],"blocks.":[89]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
