{"id":"https://openalex.org/W2125775317","doi":"https://doi.org/10.1109/apccas.2008.4746119","title":"Design and implementation of the configuration circuit for FDP FPGA","display_name":"Design and implementation of the configuration circuit for FDP FPGA","publication_year":2008,"publication_date":"2008-11-01","ids":{"openalex":"https://openalex.org/W2125775317","doi":"https://doi.org/10.1109/apccas.2008.4746119","mag":"2125775317"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2008.4746119","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2008.4746119","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043495141","display_name":"Yabin Wang","orcid":"https://orcid.org/0000-0002-7568-3518"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yabin Wang","raw_affiliation_strings":["ASIC & System State Key Lab, Fudan University, Shanghai, China","ASIC & Syst. State Key Lab., Fudan Univ., Shanghai"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ASIC & System State Key Lab, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"ASIC & Syst. State Key Lab., Fudan Univ., Shanghai","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109600761","display_name":"Xie Jing","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jing Xie","raw_affiliation_strings":["ASIC & System State Key Lab, Fudan University, 825 Zhang Heng Road, Shanghai, China","ASIC & Syst. State Key Lab., Fudan Univ., Shanghai"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ASIC & System State Key Lab, Fudan University, 825 Zhang Heng Road, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"ASIC & Syst. State Key Lab., Fudan Univ., Shanghai","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081419061","display_name":"Jinmei Lai","orcid":"https://orcid.org/0009-0003-5238-4720"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinmei Lai","raw_affiliation_strings":["ASIC & System State Key Lab, Fudan University, 825 Zhang Heng Road, Shanghai, China","ASIC & Syst. State Key Lab., Fudan Univ., Shanghai"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ASIC & System State Key Lab, Fudan University, 825 Zhang Heng Road, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"ASIC & Syst. State Key Lab., Fudan Univ., Shanghai","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108582576","display_name":"Jiarong Tong","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jiarong Tong","raw_affiliation_strings":["ASIC & System State Key Lab, Fudan University, 825 Zhang Heng Road, Shanghai, China","ASIC & Syst. State Key Lab., Fudan Univ., Shanghai"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ASIC & System State Key Lab, Fudan University, 825 Zhang Heng Road, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"ASIC & Syst. State Key Lab., Fudan Univ., Shanghai","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3814,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.70356082,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"696","last_page":"700"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12564","display_name":"Sensor Technology and Measurement Systems","score":0.9674000144004822,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12564","display_name":"Sensor Technology and Measurement Systems","score":0.9674000144004822,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9455000162124634,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9390000104904175,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7619951963424683},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7332985401153564},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.6147578954696655},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.5480948090553284},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5354922413825989},{"id":"https://openalex.org/keywords/fifo","display_name":"FIFO (computing and electronics)","score":0.5147449970245361},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4929659366607666},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.46310871839523315},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.42258864641189575},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.19279628992080688}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7619951963424683},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7332985401153564},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.6147578954696655},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.5480948090553284},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5354922413825989},{"id":"https://openalex.org/C2777145635","wikidata":"https://www.wikidata.org/wiki/Q515636","display_name":"FIFO (computing and electronics)","level":2,"score":0.5147449970245361},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4929659366607666},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.46310871839523315},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.42258864641189575},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.19279628992080688},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2008.4746119","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2008.4746119","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2054513622","https://openalex.org/W2106669582","https://openalex.org/W2539529950"],"related_works":["https://openalex.org/W4363649224","https://openalex.org/W913418521","https://openalex.org/W2544043553","https://openalex.org/W2546284597","https://openalex.org/W2348562861","https://openalex.org/W2170552397","https://openalex.org/W2349510975","https://openalex.org/W2540393334","https://openalex.org/W2390042878","https://openalex.org/W2062932566"],"abstract_inverted_index":{"This":[0,17],"paper":[1],"presents":[2],"a":[3,111],"configuration":[4,21,41,62,66,84,98,126,146,166,189],"circuit":[5,18,50,76,127,147],"used":[6,102],"in":[7,57,74,96,117,171,176,184],"the":[8,39,48,80,105,121,135,145],"FDP":[9,24,30,172,192],"(FDP:":[10],"Fu":[11],"Dan":[12],"Programmable":[13],"device)":[14],"FPGA":[15,37],"chip.":[16],"could":[19,51,133,173,180],"write":[20,52],"data":[22,28,108,169],"into":[23,128],"and":[25,124,138,179],"read":[26,106,182],"back":[27,107,183],"from":[29],"successfully.":[31],"Comparing":[32],"with":[33],"Xilinx":[34,82],"Virtex":[35],"Series":[36],"chips,":[38],"smallest":[40],"section":[42],"of":[43,89,144,191],"which":[44,100,119],"is":[45,72,94,194],"one":[46],"data-frame,":[47],"proposed":[49],"each":[53,168],"single":[54],"memory":[55],"cell":[56],"FDP,":[58,118],"providing":[59],"more":[60],"flexible":[61],"operations.":[63],"A":[64,87],"standard":[65],"interface,":[67],"Serial":[68],"Peripheral":[69],"Interface":[70],"(SPI),":[71],"added":[73],"this":[75,97,165],"to":[77,103],"replace":[78],"using":[79],"expensive":[81],"Platform":[83],"Flash":[85],"PROMs.":[86],"group":[88],"high":[90],"precise":[91],"sensitive":[92],"amplifiers":[93],"adopted":[95],"circuit,":[99,167],"are":[101],"magnify":[104],"values.":[109],"Through":[110],"novel":[112],"write/read":[113],"asynchronous":[114],"FIFO":[115],"structure":[116],"divides":[120],"external":[122,136],"interface":[123],"internal":[125,139],"two":[129],"clock":[130,137,140],"domains,":[131],"designers":[132],"set":[134],"separately.":[141],"Basic":[142],"functions":[143],"have":[148],"been":[149],"correctly":[150],"verified":[151],"by":[152],"Altera":[153],"DE2":[154],"development":[155],"board":[156],"platform.":[157],"The":[158,187],"post":[159],"layout":[160],"simulation":[161],"results":[162],"indicate":[163],"via":[164],"frame":[170],"be":[174,181],"written":[175],"4":[177],"mus,":[178],"5":[185],"mus.":[186],"total":[188],"time":[190],"chip":[193],"about":[195],"6.5":[196],"ms.":[197]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
