{"id":"https://openalex.org/W2149987122","doi":"https://doi.org/10.1109/apccas.2002.1115323","title":"Reconfigurable execution core for high performance DSP applications","display_name":"Reconfigurable execution core for high performance DSP applications","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W2149987122","doi":"https://doi.org/10.1109/apccas.2002.1115323","mag":"2149987122"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2002.1115323","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1115323","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024821102","display_name":"Amiya Kumar Rath","orcid":"https://orcid.org/0000-0002-9956-6973"},"institutions":[{"id":"https://openalex.org/I67357951","display_name":"KIIT University","ror":"https://ror.org/00k8zt527","country_code":"IN","type":"education","lineage":["https://openalex.org/I67357951"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"A.K. Rath","raw_affiliation_strings":["Kalinga Institute of Industrial Technology, Bhubaneswar"],"affiliations":[{"raw_affiliation_string":"Kalinga Institute of Industrial Technology, Bhubaneswar","institution_ids":["https://openalex.org/I67357951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025809855","display_name":"Pramod Kumar Meher","orcid":"https://orcid.org/0000-0003-0992-1159"},"institutions":[{"id":"https://openalex.org/I70699430","display_name":"Utkal University","ror":"https://ror.org/0034eez47","country_code":"IN","type":"education","lineage":["https://openalex.org/I70699430"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"P.K. Meher","raw_affiliation_strings":["Dept. of Comp. Sc & Application, Utkal University, Bhubaneswar, India"],"affiliations":[{"raw_affiliation_string":"Dept. of Comp. Sc & Application, Utkal University, Bhubaneswar, India","institution_ids":["https://openalex.org/I70699430"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5024821102"],"corresponding_institution_ids":["https://openalex.org/I67357951"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.12163202,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2","issue":null,"first_page":"509","last_page":"514"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.810949981212616},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.7413383722305298},{"id":"https://openalex.org/keywords/initialization","display_name":"Initialization","score":0.7066235542297363},{"id":"https://openalex.org/keywords/massively-parallel","display_name":"Massively parallel","score":0.6047826409339905},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5312297940254211},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5187295079231262},{"id":"https://openalex.org/keywords/convolution","display_name":"Convolution (computer science)","score":0.48380225896835327},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4828989505767822},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.46503111720085144},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.35340577363967896},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3225622773170471},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09679612517356873},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.06969469785690308}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.810949981212616},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.7413383722305298},{"id":"https://openalex.org/C114466953","wikidata":"https://www.wikidata.org/wiki/Q6034165","display_name":"Initialization","level":2,"score":0.7066235542297363},{"id":"https://openalex.org/C190475519","wikidata":"https://www.wikidata.org/wiki/Q544384","display_name":"Massively parallel","level":2,"score":0.6047826409339905},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5312297940254211},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5187295079231262},{"id":"https://openalex.org/C45347329","wikidata":"https://www.wikidata.org/wiki/Q5166604","display_name":"Convolution (computer science)","level":3,"score":0.48380225896835327},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4828989505767822},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.46503111720085144},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35340577363967896},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3225622773170471},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09679612517356873},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.06969469785690308},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2002.1115323","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1115323","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1792545593","https://openalex.org/W2102301203","https://openalex.org/W2147859829","https://openalex.org/W2168854946","https://openalex.org/W2544639424"],"related_works":["https://openalex.org/W3176564347","https://openalex.org/W3031039437","https://openalex.org/W3204184292","https://openalex.org/W1985458517","https://openalex.org/W2355833770","https://openalex.org/W3101398262","https://openalex.org/W3095877357","https://openalex.org/W10861731","https://openalex.org/W1980880153","https://openalex.org/W2169963286"],"abstract_inverted_index":{"The":[0,48],"paper":[1],"presents":[2],"an":[3],"execution":[4,52],"core":[5,53],"which":[6],"can":[7,39],"be":[8,40],"reconfigured":[9],"either":[10],"for":[11,17,58],"calculation":[12],"of":[13,19,28],"digital":[14],"convolution":[15],"or":[16],"computation":[18],"discrete":[20],"orthogonal":[21],"transform":[22],"by":[23,42],"appropriate":[24],"local":[25],"buffer":[26],"initialization":[27],"processing":[29,62],"cells.":[30],"It":[31],"is":[32],"shown":[33],"that":[34],"the":[35],"data":[36],"flow":[37],"pattern":[38],"changed":[41],"a":[43],"single":[44],"bit":[45],"control":[46],"signal.":[47],"massively":[49],"parallel":[50],"proposed":[51],"will":[54],"yield":[55],"high":[56],"throughput":[57],"multimedia":[59],"and":[60],"image":[61],"DSP":[63],"applications.":[64]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
