{"id":"https://openalex.org/W1691923927","doi":"https://doi.org/10.1109/apccas.2002.1115255","title":"Characterization and computation of Steiner wiring based on Elmore's delay model","display_name":"Characterization and computation of Steiner wiring based on Elmore's delay model","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W1691923927","doi":"https://doi.org/10.1109/apccas.2002.1115255","mag":"1691923927"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2002.1115255","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1115255","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065870863","display_name":"Satoshi Tayu","orcid":null},"institutions":[{"id":"https://openalex.org/I177738480","display_name":"Japan Advanced Institute of Science and Technology","ror":"https://ror.org/03frj4r98","country_code":"JP","type":"education","lineage":["https://openalex.org/I177738480"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"S. Tayu","raw_affiliation_strings":["School of Information Science, Japan Advanced Institute of Science and Technology, Japan","School of Information Science, Japan Advanced Institute of Sicnence and Technology, Tatsunokuchi, Ishikawa, Japan"],"affiliations":[{"raw_affiliation_string":"School of Information Science, Japan Advanced Institute of Science and Technology, Japan","institution_ids":["https://openalex.org/I177738480"]},{"raw_affiliation_string":"School of Information Science, Japan Advanced Institute of Sicnence and Technology, Tatsunokuchi, Ishikawa, Japan","institution_ids":["https://openalex.org/I177738480"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005319735","display_name":"M. Kaneko","orcid":"https://orcid.org/0000-0001-6596-1716"},"institutions":[{"id":"https://openalex.org/I177738480","display_name":"Japan Advanced Institute of Science and Technology","ror":"https://ror.org/03frj4r98","country_code":"JP","type":"education","lineage":["https://openalex.org/I177738480"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Kaneko","raw_affiliation_strings":["School of Information Science, Japan Advanced Institute of Sicnence and Technology, Tatsunokuchi, Ishikawa, Japan"],"affiliations":[{"raw_affiliation_string":"School of Information Science, Japan Advanced Institute of Sicnence and Technology, Tatsunokuchi, Ishikawa, Japan","institution_ids":["https://openalex.org/I177738480"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5065870863"],"corresponding_institution_ids":["https://openalex.org/I177738480"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12291239,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2","issue":null,"first_page":"335","last_page":"340"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/elmore-delay","display_name":"Elmore delay","score":0.9712721109390259},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.791845440864563},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7088061571121216},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6727515459060669},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5916001796722412},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.5499191284179688},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.41845205426216125},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.1670398712158203},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1542135775089264}],"concepts":[{"id":"https://openalex.org/C84434228","wikidata":"https://www.wikidata.org/wiki/Q4531332","display_name":"Elmore delay","level":4,"score":0.9712721109390259},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.791845440864563},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7088061571121216},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6727515459060669},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5916001796722412},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.5499191284179688},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.41845205426216125},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1670398712158203},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1542135775089264},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2002.1115255","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1115255","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1988808425","https://openalex.org/W2020112047","https://openalex.org/W2034999260","https://openalex.org/W2141790567","https://openalex.org/W2144677702","https://openalex.org/W2144872301","https://openalex.org/W2154363431","https://openalex.org/W3033483881","https://openalex.org/W4285719527","https://openalex.org/W6675735288"],"related_works":["https://openalex.org/W2114232017","https://openalex.org/W1927636319","https://openalex.org/W3015599398","https://openalex.org/W2792778858","https://openalex.org/W2188730438","https://openalex.org/W2373416410","https://openalex.org/W2367816239","https://openalex.org/W2101823170","https://openalex.org/W2034656493","https://openalex.org/W1875529755"],"abstract_inverted_index":{"As":[0],"a":[1,17,22,42,52,87,102,111,114],"remarkable":[2],"development":[3],"of":[4,16,44,51,62,97,113,126,158],"VLSI":[5],"technology,":[6],"gate":[7],"switching":[8],"delay":[9,15,50,72,148,162],"is":[10,31,83,136],"reduced":[11],"and":[12,58,77,81,100],"an":[13,48],"interconnection":[14,35,49,119],"net":[18,115],"comes":[19],"to":[20,33,46,116],"have":[21],"considerable":[23],"effect":[24],"on":[25,106],"the":[26,95,98,118,124,132,145,156,159],"clock":[27],"period.":[28],"Therefore,":[29],"it":[30,82],"required":[32],"minimize":[34,117],"delays":[36,61],"in":[37,68],"digital":[38],"VLSIs.":[39],"There":[40],"are":[41],"number":[43],"ways":[45],"evaluate":[47],"net,":[53],"such":[54],"as":[55,86],"cost,":[56],"radius,":[57],"Elmore's":[59,71,147,161],"delay:":[60],"those":[63],"models":[64],"can":[65],"be":[66],"computed":[67],"linear":[69],"time.":[70],"model":[73,99],"takes":[74],"both":[75],"capacitance":[76],"resistance":[78],"into":[79],"account":[80],"often":[84],"regarded":[85],"reasonable":[88],"model.":[89],"In":[90],"this":[91],"paper,":[92],"we":[93],"investigate":[94],"properties":[96,108],"construct":[101],"heuristic":[103],"algorithm":[104,129,134,154],"based":[105],"these":[107],"for":[109,143],"computing":[110],"wiring":[112],"delay.":[120],"We":[121],"also":[122],"show":[123],"effectiveness":[125],"our":[127],"proposed":[128,137,153],"by":[130,138,163],"comparing":[131],"ERT":[133],"which":[135],"Boese":[139],"et":[140],"al.":[141],"(1995)":[142],"minimizing":[144],"maximum":[146,160],"over":[149],"all":[150],"sinks.":[151],"Our":[152],"decreases":[155],"average":[157],"10-20%.":[164]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}