{"id":"https://openalex.org/W1909513197","doi":"https://doi.org/10.1109/apccas.2002.1115137","title":"Redundant transformations for BIST testability metrics-based data path allocation","display_name":"Redundant transformations for BIST testability metrics-based data path allocation","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W1909513197","doi":"https://doi.org/10.1109/apccas.2002.1115137","mag":"1909513197"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2002.1115137","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1115137","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049154222","display_name":"Laurence T. Yang","orcid":"https://orcid.org/0000-0002-7986-4244"},"institutions":[{"id":"https://openalex.org/I212119943","display_name":"University of Victoria","ror":"https://ror.org/04s5mat29","country_code":"CA","type":"education","lineage":["https://openalex.org/I212119943"]},{"id":"https://openalex.org/I197191942","display_name":"St. Francis Xavier University","ror":"https://ror.org/01wcaxs37","country_code":"CA","type":"education","lineage":["https://openalex.org/I197191942"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"L.T. Yang","raw_affiliation_strings":["Department of Computer Science, Saint Francis Xavier University, Antigonish, Canada","Department of Computer Science, University of Victoria, Victoria, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Saint Francis Xavier University, Antigonish, Canada","institution_ids":["https://openalex.org/I197191942"]},{"raw_affiliation_string":"Department of Computer Science, University of Victoria, Victoria, Canada","institution_ids":["https://openalex.org/I212119943"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044762563","display_name":"J.C. Muzio","orcid":null},"institutions":[{"id":"https://openalex.org/I212119943","display_name":"University of Victoria","ror":"https://ror.org/04s5mat29","country_code":"CA","type":"education","lineage":["https://openalex.org/I212119943"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"J. Muzio","raw_affiliation_strings":["Department of Computer Science, University of Victoria, Victoria, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Victoria, Victoria, Canada","institution_ids":["https://openalex.org/I212119943"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5049154222"],"corresponding_institution_ids":["https://openalex.org/I197191942","https://openalex.org/I212119943"],"apc_list":null,"apc_paid":null,"fwci":0.2562,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.38876059,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2","issue":null,"first_page":"119","last_page":"123"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.7955741882324219},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.7429242134094238},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7008074522018433},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5758919715881348},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.5685524344444275},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5152616500854492},{"id":"https://openalex.org/keywords/metric","display_name":"Metric (unit)","score":0.49612531065940857},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.22013115882873535},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.16221266984939575},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1457948386669159}],"concepts":[{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.7955741882324219},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.7429242134094238},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7008074522018433},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5758919715881348},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.5685524344444275},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5152616500854492},{"id":"https://openalex.org/C176217482","wikidata":"https://www.wikidata.org/wiki/Q860554","display_name":"Metric (unit)","level":2,"score":0.49612531065940857},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.22013115882873535},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.16221266984939575},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1457948386669159},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2002.1115137","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1115137","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5400000214576721,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1583548160","https://openalex.org/W1628270187","https://openalex.org/W1994188141","https://openalex.org/W2017276983","https://openalex.org/W2052900688","https://openalex.org/W2100590846","https://openalex.org/W2101492865","https://openalex.org/W2103538449","https://openalex.org/W2105607535","https://openalex.org/W2112447814","https://openalex.org/W2121517293","https://openalex.org/W2147197770","https://openalex.org/W2147402582","https://openalex.org/W2148663017","https://openalex.org/W2149020879","https://openalex.org/W2155035339","https://openalex.org/W2164493372","https://openalex.org/W2170235199","https://openalex.org/W2172154421","https://openalex.org/W2460458470","https://openalex.org/W2533585991","https://openalex.org/W3143912150","https://openalex.org/W4249241529","https://openalex.org/W6677921749","https://openalex.org/W6728769559"],"related_works":["https://openalex.org/W2157191248","https://openalex.org/W2107525390","https://openalex.org/W3141833020","https://openalex.org/W2150046587","https://openalex.org/W2164493372","https://openalex.org/W2114980936","https://openalex.org/W4249526199","https://openalex.org/W4245595174","https://openalex.org/W2115513740","https://openalex.org/W2539511314"],"abstract_inverted_index":{"In":[0,21],"our":[1,50,66,70],"previous":[2,51,71],"works,":[3],"we":[4,25,61],"described":[5],"a":[6,57],"BIST":[7],"testability":[8],"metric-based":[9],"high-level":[10],"data":[11,46,52],"path":[12,53],"allocation":[13,54],"algorithm":[14],"to":[15,41,48],"facilitate":[16],"Built-In":[17],"Self-Test":[18],"(BIST)":[19],"designs.":[20],"the":[22,45,63],"present":[23],"paper,":[24],"make":[26],"use":[27],"of":[28,31,59,65],"two":[29],"types":[30],"redundant":[32],"transformations,":[33],"which":[34],"add":[35],"redundancy":[36],"that":[37],"improves":[38],"test":[39],"resources":[40],"be":[42],"shared":[43],"in":[44],"path,":[47],"improve":[49],"algorithm.":[55],"With":[56],"variety":[58],"benchmarks,":[60],"demonstrate":[62],"advantage":[64],"approach":[67],"compared":[68],"with":[69],"and":[72],"other":[73],"conventional":[74],"approaches.":[75]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
