{"id":"https://openalex.org/W1623061273","doi":"https://doi.org/10.1109/apccas.2002.1115136","title":"Chip size estimation based on wiring area","display_name":"Chip size estimation based on wiring area","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W1623061273","doi":"https://doi.org/10.1109/apccas.2002.1115136","mag":"1623061273"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2002.1115136","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1115136","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039235243","display_name":"Yukiko Kubo","orcid":null},"institutions":[{"id":"https://openalex.org/I17056963","display_name":"The University of Kitakyushu","ror":"https://ror.org/03mfefw72","country_code":"JP","type":"education","lineage":["https://openalex.org/I17056963"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Y. Kubo","raw_affiliation_strings":["Department of Information and Media Sciences, University of Kitakyushu, Fukuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Information and Media Sciences, University of Kitakyushu, Fukuoka, Japan","institution_ids":["https://openalex.org/I17056963"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000531897","display_name":"Shigetoshi Nakatake","orcid":null},"institutions":[{"id":"https://openalex.org/I17056963","display_name":"The University of Kitakyushu","ror":"https://ror.org/03mfefw72","country_code":"JP","type":"education","lineage":["https://openalex.org/I17056963"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"S. Nakatake","raw_affiliation_strings":["Department of Information and Media Sciences, University of Kitakyushu, Fukuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Information and Media Sciences, University of Kitakyushu, Fukuoka, Japan","institution_ids":["https://openalex.org/I17056963"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002482954","display_name":"Yoji Kajitani","orcid":null},"institutions":[{"id":"https://openalex.org/I17056963","display_name":"The University of Kitakyushu","ror":"https://ror.org/03mfefw72","country_code":"JP","type":"education","lineage":["https://openalex.org/I17056963"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Y. Kajitani","raw_affiliation_strings":["Department of Information and Media Sciences, University of Kitakyushu, Fukuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Information and Media Sciences, University of Kitakyushu, Fukuoka, Japan","institution_ids":["https://openalex.org/I17056963"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025734531","display_name":"Masahiro Kawakita","orcid":null},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Kawakita","raw_affiliation_strings":["Semiconductor Company, Toshiba Corporation, Yokohama, Kanagawa, Japan"],"affiliations":[{"raw_affiliation_string":"Semiconductor Company, Toshiba Corporation, Yokohama, Kanagawa, Japan","institution_ids":["https://openalex.org/I1292669757"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5039235243"],"corresponding_institution_ids":["https://openalex.org/I17056963"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.11485497,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"2","issue":null,"first_page":"113","last_page":"118"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.7783116698265076},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6805254220962524},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5889995098114014},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.5611394047737122},{"id":"https://openalex.org/keywords/planar-graph","display_name":"Planar graph","score":0.5242151021957397},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5062662363052368},{"id":"https://openalex.org/keywords/dual-graph","display_name":"Dual graph","score":0.48028799891471863},{"id":"https://openalex.org/keywords/page-layout","display_name":"Page layout","score":0.42976099252700806},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.42373257875442505},{"id":"https://openalex.org/keywords/planar","display_name":"Planar","score":0.42347899079322815},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4172297418117523},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3532944321632385},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3167656660079956},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.18670743703842163},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.14741629362106323},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09210819005966187}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.7783116698265076},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6805254220962524},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5889995098114014},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.5611394047737122},{"id":"https://openalex.org/C101837359","wikidata":"https://www.wikidata.org/wiki/Q547823","display_name":"Planar graph","level":3,"score":0.5242151021957397},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5062662363052368},{"id":"https://openalex.org/C169827030","wikidata":"https://www.wikidata.org/wiki/Q2294516","display_name":"Dual graph","level":4,"score":0.48028799891471863},{"id":"https://openalex.org/C188985296","wikidata":"https://www.wikidata.org/wiki/Q868954","display_name":"Page layout","level":2,"score":0.42976099252700806},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.42373257875442505},{"id":"https://openalex.org/C134786449","wikidata":"https://www.wikidata.org/wiki/Q3391255","display_name":"Planar","level":2,"score":0.42347899079322815},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4172297418117523},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3532944321632385},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3167656660079956},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.18670743703842163},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.14741629362106323},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09210819005966187},{"id":"https://openalex.org/C112698675","wikidata":"https://www.wikidata.org/wiki/Q37038","display_name":"Advertising","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C121684516","wikidata":"https://www.wikidata.org/wiki/Q7600677","display_name":"Computer graphics (images)","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2002.1115136","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1115136","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities","score":0.7200000286102295}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1987786682","https://openalex.org/W2079644256","https://openalex.org/W2108092114","https://openalex.org/W2136910485","https://openalex.org/W2141235761","https://openalex.org/W2154462472","https://openalex.org/W4247948903","https://openalex.org/W4302087205","https://openalex.org/W6647386927"],"related_works":["https://openalex.org/W2246199414","https://openalex.org/W4300508906","https://openalex.org/W2124495928","https://openalex.org/W2096129555","https://openalex.org/W2097517502","https://openalex.org/W2129355781","https://openalex.org/W4363620137","https://openalex.org/W2052733504","https://openalex.org/W2152479836","https://openalex.org/W2161137937"],"abstract_inverted_index":{"The":[0,30,111],"placement":[1,60],"of":[2,95,107],"modules":[3],"must":[4],"be":[5,138],"designed":[6],"considering":[7],"the":[8,35,39,42,66,75,87,93,98,105,108,116,129],"routability":[9],"and":[10,38,81],"area":[11],"reduction":[12],"simultaneously.":[13],"But":[14],"as":[15],"they":[16,70],"are":[17,51,71,79,89,134],"rather":[18],"conflicting":[19],"aims,":[20],"it":[21],"is":[22,32,58,101,113],"not":[23],"easy":[24],"to":[25,54,83,104,127,137],"devise":[26],"a":[27],"consistent":[28,59],"method.":[29],"wiring":[31],"done":[33],"on":[34,41,74],"routing":[36,99],"graph":[37,100],"compaction":[40,43,109],"graph.":[44,110],"Therefore,":[45],"only":[46,123],"if":[47,69],"these":[48,77],"two":[49],"graphs":[50,78],"so":[52],"defined":[53],"reflect":[55],"each":[56,84],"other,":[57],"possible.":[61],"This":[62],"paper":[63,122],"points":[64],"out":[65],"fact":[67],"that":[68],"constructed":[72],"based":[73],"floorplan,":[76],"planar":[80],"dual":[82],"other.":[85],"Since":[86],"edges":[88],"in":[90,97],"one-to-one":[91],"correspondence,":[92],"congestion":[94],"wires":[96],"directly":[102],"transformed":[103],"length":[106],"idea":[112],"used":[114],"for":[115],"whole":[117],"layout":[118],"design":[119],"but":[120],"this":[121],"describes":[124],"an":[125],"application":[126],"predict":[128],"chip":[130],"area.":[131],"Some":[132],"experiments":[133],"also":[135],"shown":[136],"promising.":[139]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}