{"id":"https://openalex.org/W2149635558","doi":"https://doi.org/10.1109/apccas.2002.1115037","title":"Incorporating area-time flexibility to a binary signed-digit adder","display_name":"Incorporating area-time flexibility to a binary signed-digit adder","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2149635558","doi":"https://doi.org/10.1109/apccas.2002.1115037","mag":"2149635558"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2002.1115037","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1115037","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002694277","display_name":"Siew-Kei Lam","orcid":"https://orcid.org/0000-0002-8346-2635"},"institutions":[{"id":"https://openalex.org/I4210145666","display_name":"Embedded Systems (United States)","ror":"https://ror.org/04742eh45","country_code":"US","type":"company","lineage":["https://openalex.org/I4210145666"]},{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG","US"],"is_corresponding":true,"raw_author_name":"S.K. Lam","raw_affiliation_strings":["Centre for High Performance Embedded Systems, Nanyang Technological University, Nanyang Avenue, SINGAPORE"],"affiliations":[{"raw_affiliation_string":"Centre for High Performance Embedded Systems, Nanyang Technological University, Nanyang Avenue, SINGAPORE","institution_ids":["https://openalex.org/I172675005","https://openalex.org/I4210145666"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070475093","display_name":"Thambipillai Srikanthan","orcid":"https://orcid.org/0000-0003-3664-4345"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]},{"id":"https://openalex.org/I4210145666","display_name":"Embedded Systems (United States)","ror":"https://ror.org/04742eh45","country_code":"US","type":"company","lineage":["https://openalex.org/I4210145666"]}],"countries":["SG","US"],"is_corresponding":false,"raw_author_name":"T. Srikanthan","raw_affiliation_strings":["Centre for High Performance Embedded Systems, Nanyang Technological University, Nanyang Avenue, SINGAPORE"],"affiliations":[{"raw_affiliation_string":"Centre for High Performance Embedded Systems, Nanyang Technological University, Nanyang Avenue, SINGAPORE","institution_ids":["https://openalex.org/I172675005","https://openalex.org/I4210145666"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073215837","display_name":"nbspChandra Bihari Goyal","orcid":"https://orcid.org/0009-0005-3985-0322"},"institutions":[{"id":"https://openalex.org/I110166357","display_name":"University of Delhi","ror":"https://ror.org/04gzb2213","country_code":"IN","type":"education","lineage":["https://openalex.org/I110166357"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"N. Goyal","raw_affiliation_strings":["Department of Computer Engineering, University of Delhi, New Delhi, INDIA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, University of Delhi, New Delhi, INDIA","institution_ids":["https://openalex.org/I110166357"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102714548","display_name":"Nancy Tyagi","orcid":"https://orcid.org/0009-0006-9813-9351"},"institutions":[{"id":"https://openalex.org/I110166357","display_name":"University of Delhi","ror":"https://ror.org/04gzb2213","country_code":"IN","type":"education","lineage":["https://openalex.org/I110166357"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"N. Tyagi","raw_affiliation_strings":["Department of Computer Engineering, University of Delhi, New Delhi, INDIA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, University of Delhi, New Delhi, INDIA","institution_ids":["https://openalex.org/I110166357"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5002694277"],"corresponding_institution_ids":["https://openalex.org/I172675005","https://openalex.org/I4210145666"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.21698113,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"485","last_page":"489"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7938966155052185},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7674400806427002},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6569607257843018},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.64494389295578},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.6063015460968018},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.5591040849685669},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5473239421844482},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.44339635968208313},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.42492297291755676},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.42262470722198486},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3257756233215332},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.16690507531166077},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16179275512695312},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.1341572403907776},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.09911641478538513},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07954126596450806},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.06986990571022034}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7938966155052185},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7674400806427002},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6569607257843018},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.64494389295578},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.6063015460968018},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.5591040849685669},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5473239421844482},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.44339635968208313},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.42492297291755676},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.42262470722198486},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3257756233215332},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.16690507531166077},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16179275512695312},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.1341572403907776},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.09911641478538513},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07954126596450806},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.06986990571022034},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2002.1115037","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1115037","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1584008964","https://openalex.org/W1587217691","https://openalex.org/W1822244604","https://openalex.org/W1973623217","https://openalex.org/W2019268842","https://openalex.org/W2044829853","https://openalex.org/W2109911029","https://openalex.org/W2110801419","https://openalex.org/W2131256658","https://openalex.org/W6634851982","https://openalex.org/W6635218997"],"related_works":["https://openalex.org/W4390550886","https://openalex.org/W3217463396","https://openalex.org/W2790557758","https://openalex.org/W2516396101","https://openalex.org/W2183015194","https://openalex.org/W2015155483","https://openalex.org/W2134640991","https://openalex.org/W3027318491","https://openalex.org/W1979789826","https://openalex.org/W1986774039"],"abstract_inverted_index":{"Computer":[0],"arithmetic":[1],"operations":[2],"based":[3],"on":[4],"redundant":[5],"signed-digit":[6],"representation":[7],"systems":[8],"such":[9],"as":[10],"the":[11,65,70,77],"BSD":[12,40],"(binary":[13],"signed-digit)":[14],"number":[15],"system":[16],"execute":[17],"faster":[18],"due":[19],"to":[20],"limited":[21],"carry":[22],"propagation":[23],"additions.":[24],"In":[25],"this":[26],"paper,":[27],"area-time":[28,89],"measures":[29],"for":[30,88],"fully":[31,66],"parallel,":[32],"serial":[33,78],"and":[34,79],"pipelined":[35,80],"implementations":[36,84],"of":[37],"a":[38],"well-known":[39],"addition":[41],"technique":[42],"are":[43],"presented.":[44],"All":[45],"three":[46],"versions":[47],"were":[48],"synthesized":[49],"at":[50],"gate":[51],"level":[52],"using":[53],"0.35":[54],"/spl":[55],"mu/m":[56],"CMOS":[57],"cell-based":[58],"libraries.":[59],"Our":[60],"results":[61],"show":[62],"that":[63,85],"while":[64],"parallel":[67],"method":[68],"provides":[69],"fastest":[71],"with":[72],"highest":[73],"area":[74],"complexity,":[75],"both":[76],"approaches":[81],"facilitate":[82],"scalable":[83],"lend":[86],"well":[87],"optimal":[90],"solutions":[91],"in":[92],"VLSI.":[93]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}