{"id":"https://openalex.org/W1959215105","doi":"https://doi.org/10.1109/apccas.2002.1115036","title":"A rapid prototyping embedded system platform and its HW/SW communication interface generation and verification","display_name":"A rapid prototyping embedded system platform and its HW/SW communication interface generation and verification","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W1959215105","doi":"https://doi.org/10.1109/apccas.2002.1115036","mag":"1959215105"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2002.1115036","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1115036","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019252212","display_name":"Yin\u2010Tsung Hwang","orcid":"https://orcid.org/0000-0001-9233-0477"},"institutions":[{"id":"https://openalex.org/I75357094","display_name":"National Yunlin University of Science and Technology","ror":"https://ror.org/04qkq2m54","country_code":"TW","type":"education","lineage":["https://openalex.org/I75357094"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Yin-Tsung Hwang","raw_affiliation_strings":["Institute of Electronic Engineering and Information Science, National Yunlin University of Science and Technology, Taiwan","Inst. of Electron. Eng. & Inf. Sci., Nat. Yunlin Univ. of Sci. & Technol., Taiwan"],"affiliations":[{"raw_affiliation_string":"Institute of Electronic Engineering and Information Science, National Yunlin University of Science and Technology, Taiwan","institution_ids":["https://openalex.org/I75357094"]},{"raw_affiliation_string":"Inst. of Electron. Eng. & Inf. Sci., Nat. Yunlin Univ. of Sci. & Technol., Taiwan","institution_ids":["https://openalex.org/I75357094"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113518620","display_name":"Cheng-Ji Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I75357094","display_name":"National Yunlin University of Science and Technology","ror":"https://ror.org/04qkq2m54","country_code":"TW","type":"education","lineage":["https://openalex.org/I75357094"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Cheng-Ji Chang","raw_affiliation_strings":["Institute of Electronic Engineering and Information Science, National Yunlin University of Science and Technology, Taiwan","Inst. of Electron. Eng. & Inf. Sci., Nat. Yunlin Univ. of Sci. & Technol., Taiwan"],"affiliations":[{"raw_affiliation_string":"Institute of Electronic Engineering and Information Science, National Yunlin University of Science and Technology, Taiwan","institution_ids":["https://openalex.org/I75357094"]},{"raw_affiliation_string":"Inst. of Electron. Eng. & Inf. Sci., Nat. Yunlin Univ. of Sci. & Technol., Taiwan","institution_ids":["https://openalex.org/I75357094"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100294289","display_name":"Bor-Liang Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I75357094","display_name":"National Yunlin University of Science and Technology","ror":"https://ror.org/04qkq2m54","country_code":"TW","type":"education","lineage":["https://openalex.org/I75357094"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Bor-Liang Chen","raw_affiliation_strings":["Institute of Electronic Engineering and Information Science, National Yunlin University of Science and Technology, Taiwan","Inst. of Electron. Eng. & Inf. Sci., Nat. Yunlin Univ. of Sci. & Technol., Taiwan"],"affiliations":[{"raw_affiliation_string":"Institute of Electronic Engineering and Information Science, National Yunlin University of Science and Technology, Taiwan","institution_ids":["https://openalex.org/I75357094"]},{"raw_affiliation_string":"Inst. of Electron. Eng. & Inf. Sci., Nat. Yunlin Univ. of Sci. & Technol., Taiwan","institution_ids":["https://openalex.org/I75357094"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5019252212"],"corresponding_institution_ids":["https://openalex.org/I75357094"],"apc_list":null,"apc_paid":null,"fwci":0.2562,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.39337952,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":"1","issue":null,"first_page":"481","last_page":"484"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9932000041007996,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7341470718383789},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7266494035720825},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7052744030952454},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.6022706031799316},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.569328248500824},{"id":"https://openalex.org/keywords/rapid-prototyping","display_name":"Rapid prototyping","score":0.5582985281944275},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5565377473831177},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.5551078915596008},{"id":"https://openalex.org/keywords/communications-system","display_name":"Communications system","score":0.45327743887901306},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.42392587661743164},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.41220107674598694},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3375796377658844},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.22381597757339478},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17054793238639832}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7341470718383789},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7266494035720825},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7052744030952454},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.6022706031799316},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.569328248500824},{"id":"https://openalex.org/C2780395129","wikidata":"https://www.wikidata.org/wiki/Q1128971","display_name":"Rapid prototyping","level":2,"score":0.5582985281944275},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5565377473831177},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5551078915596008},{"id":"https://openalex.org/C101765175","wikidata":"https://www.wikidata.org/wiki/Q577764","display_name":"Communications system","level":2,"score":0.45327743887901306},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42392587661743164},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.41220107674598694},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3375796377658844},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.22381597757339478},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17054793238639832},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2002.1115036","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1115036","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1526454193","https://openalex.org/W1979486932","https://openalex.org/W2100519472","https://openalex.org/W4248688512"],"related_works":["https://openalex.org/W2535403365","https://openalex.org/W1486911645","https://openalex.org/W2016926482","https://openalex.org/W2129671278","https://openalex.org/W2975035977","https://openalex.org/W2138506581","https://openalex.org/W3147044877","https://openalex.org/W2545414197","https://openalex.org/W2139939460","https://openalex.org/W2096051567"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"first":[4],"present":[5,27],"a":[6],"DSP+FPGA":[7],"rapid":[8],"prototyping":[9],"system":[10,29,96,107],"platform":[11],"(RAPSP)":[12],"capable":[13],"of":[14,36,61],"implementing":[15],"and":[16,32,49,87],"emulating":[17],"various":[18],"embedded":[19],"systems":[20],"based":[21],"on":[22,75,110],"HW/SW":[23,72],"codesign.":[24],"We":[25],"secondly":[26],"the":[28,33,37,41,45,50,71,76],"design":[30],"flow":[31,98],"verification":[34],"methodology":[35],"platform.":[38,77],"To":[39],"facilitate":[40],"communication":[42,55,63,73],"efficiency":[43],"between":[44],"DSP":[46,86],"(SW":[47],"section)":[48],"FPGA":[51,88],"arrays":[52],"(HW":[53],"section),":[54],"buffers":[56],"are":[57],"employed.":[58],"A":[59,94],"library":[60],"parameterized":[62],"interface":[64],"modules":[65],"was":[66],"also":[67,100],"developed":[68,83],"to":[69],"support":[70],"designs":[74,89],"Transaction":[78],"level":[79],"simulation":[80],"models":[81],"were":[82],"so":[84],"that":[85],"can":[90],"be":[91],"verified":[92],"together.":[93],"practical":[95],"design/verification":[97],"is":[99,112],"developed.":[101],"Finally,":[102],"an":[103],"LD-CELP":[104],"speech":[105],"compression":[106],"implementation":[108],"example":[109],"RAPSP":[111],"described.":[113]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}