{"id":"https://openalex.org/W1584773828","doi":"https://doi.org/10.1109/apccas.2002.1114944","title":"Analog low-voltage current-mode implementation of digital logic gates","display_name":"Analog low-voltage current-mode implementation of digital logic gates","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W1584773828","doi":"https://doi.org/10.1109/apccas.2002.1114944","mag":"1584773828"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2002.1114944","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1114944","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070167809","display_name":"Muhammad Taher Abuelma\u2019atti","orcid":"https://orcid.org/0000-0002-0471-9675"},"institutions":[{"id":"https://openalex.org/I134085113","display_name":"King Fahd University of Petroleum and Minerals","ror":"https://ror.org/03yez3163","country_code":"SA","type":"education","lineage":["https://openalex.org/I134085113"]}],"countries":["SA"],"is_corresponding":true,"raw_author_name":"M.T. Abuelma'atti","raw_affiliation_strings":["King Fahd University of Petroleum and Minerals, Dhahran, Saudi Arabia","[King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia]"],"affiliations":[{"raw_affiliation_string":"King Fahd University of Petroleum and Minerals, Dhahran, Saudi Arabia","institution_ids":["https://openalex.org/I134085113"]},{"raw_affiliation_string":"[King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia]","institution_ids":["https://openalex.org/I134085113"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5070167809"],"corresponding_institution_ids":["https://openalex.org/I134085113"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.15927419,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"1","issue":null,"first_page":"233","last_page":"236"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.697030782699585},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6434727907180786},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.627444863319397},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.6269288659095764},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.5913552641868591},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5788557529449463},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5767315030097961},{"id":"https://openalex.org/keywords/xor-gate","display_name":"XOR gate","score":0.5346505045890808},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.5109966993331909},{"id":"https://openalex.org/keywords/current-mode-logic","display_name":"Current-mode logic","score":0.5102124214172363},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5004732608795166},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.4726528227329254},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.44007349014282227},{"id":"https://openalex.org/keywords/resistor\u2013transistor-logic","display_name":"Resistor\u2013transistor logic","score":0.4365854561328888},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3906063735485077},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.36765843629837036},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3545936942100525},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.32085371017456055},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23524394631385803},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.22338929772377014}],"concepts":[{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.697030782699585},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6434727907180786},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.627444863319397},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.6269288659095764},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.5913552641868591},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5788557529449463},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5767315030097961},{"id":"https://openalex.org/C28495749","wikidata":"https://www.wikidata.org/wiki/Q155516","display_name":"XOR gate","level":3,"score":0.5346505045890808},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.5109966993331909},{"id":"https://openalex.org/C2780295579","wikidata":"https://www.wikidata.org/wiki/Q5195108","display_name":"Current-mode logic","level":3,"score":0.5102124214172363},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5004732608795166},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.4726528227329254},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.44007349014282227},{"id":"https://openalex.org/C180405849","wikidata":"https://www.wikidata.org/wiki/Q173464","display_name":"Resistor\u2013transistor logic","level":5,"score":0.4365854561328888},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3906063735485077},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.36765843629837036},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3545936942100525},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.32085371017456055},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23524394631385803},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.22338929772377014},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2002.1114944","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1114944","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6600000262260437}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322323","display_name":"King Fahd University of Petroleum and Minerals","ror":"https://ror.org/03yez3163"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1530621902","https://openalex.org/W1537352836","https://openalex.org/W1968538198","https://openalex.org/W1973935750","https://openalex.org/W2071180714","https://openalex.org/W2097161792","https://openalex.org/W2266281062","https://openalex.org/W2275803487","https://openalex.org/W6631831516","https://openalex.org/W6632228782","https://openalex.org/W6692996694","https://openalex.org/W6694372589"],"related_works":["https://openalex.org/W2554150716","https://openalex.org/W2049889603","https://openalex.org/W2084524856","https://openalex.org/W2082591327","https://openalex.org/W2102653533","https://openalex.org/W2580743037","https://openalex.org/W2020551446","https://openalex.org/W4240911253","https://openalex.org/W2058718664","https://openalex.org/W2060833522"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"a":[3,58],"new":[4],"approach":[5],"is":[6,38,51,72],"introduced":[7],"for":[8,60],"implementing":[9],"the":[10,20,34,47,55,64],"basic":[11,35],"logic":[12,21,36,65],"functions":[13,22,37,66],"using":[14,28],"analog":[15],"current-mode":[16],"techniques.":[17],"By":[18],"expanding":[19],"in":[23,45],"power":[24],"series":[25],"expressions,":[26],"and":[27,30,70],"summers":[29],"multipliers,":[31],"realization":[32,62],"of":[33,49,63],"simplified.":[39],"Since":[40],"no":[41],"transistors":[42],"are":[43,81],"working":[44],"saturation,":[46],"problem":[48],"fan-out":[50],"alleviated.":[52],"To":[53],"illustrate":[54],"proposed":[56],"technique,":[57],"circuit":[59],"simultaneous":[61],"NOT,":[67],"OR,":[68],"NAND":[69],"XOR":[71],"considered.":[73],"SPICE":[74],"simulation":[75],"results,":[76],"obtained":[77],"with":[78],"3V":[79],"supply,":[80],"included.":[82]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}