{"id":"https://openalex.org/W2163776132","doi":"https://doi.org/10.1109/apccas.2002.1114939","title":"Design and evaluation of high performance microprocessor with reconfigurable on-chip memory","display_name":"Design and evaluation of high performance microprocessor with reconfigurable on-chip memory","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2163776132","doi":"https://doi.org/10.1109/apccas.2002.1114939","mag":"2163776132"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2002.1114939","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1114939","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049139401","display_name":"T. Ohneda","orcid":null},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"T. Ohneda","raw_affiliation_strings":["Development Center, Toshiba Corporation, Japan"],"affiliations":[{"raw_affiliation_string":"Development Center, Toshiba Corporation, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103017591","display_name":"Masaaki Kondo","orcid":"https://orcid.org/0000-0002-6025-8738"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Kondo","raw_affiliation_strings":["Research Center for Advanced Science and Technology, University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Research Center for Advanced Science and Technology, University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015068403","display_name":"Masayuki Imai","orcid":"https://orcid.org/0000-0002-1400-7794"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Imai","raw_affiliation_strings":["Research Center for Advanced Science and Technology, University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Research Center for Advanced Science and Technology, University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090578339","display_name":"Hiroshi Nakamura","orcid":"https://orcid.org/0009-0005-6505-1903"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"H. Nakamura","raw_affiliation_strings":["Research Center for Advanced Science and Technology, University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Research Center for Advanced Science and Technology, University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5049139401"],"corresponding_institution_ids":["https://openalex.org/I1292669757"],"apc_list":null,"apc_paid":null,"fwci":0.3199,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.44670051,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"211","last_page":"216"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8099881410598755},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.629645824432373},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6191765069961548},{"id":"https://openalex.org/keywords/pipeline-burst-cache","display_name":"Pipeline burst cache","score":0.5264773368835449},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.5173534750938416},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5125465393066406},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.48854002356529236},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.48301395773887634},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.46430423855781555},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4553923010826111},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.4533230662345886},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.441528856754303},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4233081042766571},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42014414072036743},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4162983298301697},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3745914101600647},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3480132520198822},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.29795029759407043},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2638006806373596}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8099881410598755},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.629645824432373},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6191765069961548},{"id":"https://openalex.org/C157547923","wikidata":"https://www.wikidata.org/wiki/Q7197276","display_name":"Pipeline burst cache","level":5,"score":0.5264773368835449},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.5173534750938416},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5125465393066406},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.48854002356529236},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.48301395773887634},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.46430423855781555},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4553923010826111},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.4533230662345886},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.441528856754303},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4233081042766571},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42014414072036743},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4162983298301697},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3745914101600647},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3480132520198822},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.29795029759407043},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2638006806373596},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/apccas.2002.1114939","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1114939","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.104.6766","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.104.6766","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.hal.rcast.u-tokyo.ac.jp/~nakamura/papers/apccas02.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7300000190734863}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W307918303","https://openalex.org/W1500389415","https://openalex.org/W1957395430","https://openalex.org/W2032881466","https://openalex.org/W2100913437","https://openalex.org/W2112833506","https://openalex.org/W2142033140","https://openalex.org/W6629801906","https://openalex.org/W6631615826","https://openalex.org/W6658757725"],"related_works":["https://openalex.org/W2149371164","https://openalex.org/W3108993429","https://openalex.org/W2007929622","https://openalex.org/W2998091606","https://openalex.org/W1982632559","https://openalex.org/W2782503170","https://openalex.org/W2047684617","https://openalex.org/W2041174925","https://openalex.org/W4233816696","https://openalex.org/W1974120505"],"abstract_inverted_index":{"The":[0,103],"performance":[1,14,115],"gap":[2],"between":[3],"processor":[4,27,38,90],"and":[5,91,100],"main":[6,44],"memory":[7,34,45],"is":[8,52,64,127],"serious":[9],"problem":[10],"especially":[11],"in":[12,46],"high":[13],"computing.":[15],"In":[16,73],"order":[17],"to":[18,48,66,70],"overcome":[19],"this":[20,74],"problem,":[21],"we":[22,76],"have":[23],"proposed":[24],"a":[25,37,41,58,78],"new":[26],"architecture":[28,120],"called":[29],"SCIMA,":[30],"which":[31],"integrates":[32],"software-controllable":[33],"(SCM)":[35],"into":[36],"chip":[39],"as":[40,54],"part":[42],"of":[43,57,81,87,95,125],"addition":[47],"ordinary":[49],"cache.":[50],"SCIMA":[51,82,108,126],"defined":[53],"an":[55],"extension":[56,97],"general":[59],"microprocessor":[60],"whose":[61],"load/store":[62,79],"unit":[63,80,86],"extended":[65],"control":[67],"data":[68],"accesses":[69],"the":[71,85,93,96,122],"SCM.":[72],"paper,":[75],"present":[77],"by":[83],"extending":[84],"MIPS":[88],"R10000":[89],"evaluate":[92],"impact":[94],"on":[98],"area":[99],"clock":[101],"frequency.":[102],"evaluation":[104],"results":[105],"reveal":[106],"that":[107],"achieves":[109],"1.5":[110],"-":[111],"10":[112],"times":[113],"higher":[114],"compared":[116],"with":[117],"cache":[118],"based":[119],"although":[121],"cycle":[123],"time":[124],"5.7%":[128],"longer.":[129]},"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}