{"id":"https://openalex.org/W1890046599","doi":"https://doi.org/10.1109/apccas.2002.1114936","title":"Memory allocation method for indirect addressing with an index register","display_name":"Memory allocation method for indirect addressing with an index register","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W1890046599","doi":"https://doi.org/10.1109/apccas.2002.1114936","mag":"1890046599"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2002.1114936","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1114936","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111521488","display_name":"Yoshiyuki Kaneko","orcid":null},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Y. Kaneko","raw_affiliation_strings":["Department of Information Processing, Tokyo Institute of Technology, Yokohama, Japan","Dept. of Inf. Process., Tokyo Inst. of Technol., Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Information Processing, Tokyo Institute of Technology, Yokohama, Japan","institution_ids":["https://openalex.org/I114531698"]},{"raw_affiliation_string":"Dept. of Inf. Process., Tokyo Inst. of Technol., Yokohama, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112415065","display_name":"Nobuhiko Sugino","orcid":null},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"N. Sugino","raw_affiliation_strings":["Department of Information Processing, Tokyo Institute of Technology, Yokohama, Japan","Dept. of Inf. Process., Tokyo Inst. of Technol., Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Information Processing, Tokyo Institute of Technology, Yokohama, Japan","institution_ids":["https://openalex.org/I114531698"]},{"raw_affiliation_string":"Dept. of Inf. Process., Tokyo Inst. of Technol., Yokohama, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026294946","display_name":"Akinori Nishihara","orcid":"https://orcid.org/0000-0002-0191-4328"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"A. Nishihara","raw_affiliation_strings":["Department of Information Processing, Tokyo Institute of Technology, Yokohama, Japan","Dept. of Inf. Process., Tokyo Inst. of Technol., Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Information Processing, Tokyo Institute of Technology, Yokohama, Japan","institution_ids":["https://openalex.org/I114531698"]},{"raw_affiliation_string":"Dept. of Inf. Process., Tokyo Inst. of Technol., Yokohama, Japan","institution_ids":["https://openalex.org/I114531698"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5111521488"],"corresponding_institution_ids":["https://openalex.org/I114531698"],"apc_list":null,"apc_paid":null,"fwci":0.9602,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.67766497,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"199","last_page":"202"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8353432416915894},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.7541285753250122},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.7162383794784546},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5495808720588684},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5181678533554077},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.45627114176750183},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.41392382979393005},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.34046849608421326},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3339710235595703},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2542757987976074},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.23497194051742554},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10025498270988464},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07886311411857605}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8353432416915894},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.7541285753250122},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.7162383794784546},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5495808720588684},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5181678533554077},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.45627114176750183},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.41392382979393005},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.34046849608421326},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3339710235595703},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2542757987976074},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.23497194051742554},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10025498270988464},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07886311411857605},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/apccas.2002.1114936","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1114936","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:t2r2.star.titech.ac.jp:50171460","is_oa":false,"landing_page_url":"http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100636508","pdf_url":null,"source":{"id":"https://openalex.org/S4377196385","display_name":"Tokyo Tech Research Repository (Tokyo Institute of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I114531698","host_organization_name":"Tokyo Institute of Technology","host_organization_lineage":["https://openalex.org/I114531698"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference Paper"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W359031792","https://openalex.org/W384356085","https://openalex.org/W612002107","https://openalex.org/W1672449015","https://openalex.org/W1890046599","https://openalex.org/W2104762307","https://openalex.org/W2482688006","https://openalex.org/W6612167208","https://openalex.org/W6613013988"],"related_works":["https://openalex.org/W4297672591","https://openalex.org/W4390073573","https://openalex.org/W2155935413","https://openalex.org/W2755854447","https://openalex.org/W2282591083","https://openalex.org/W2035414676","https://openalex.org/W2070566991","https://openalex.org/W2065941861","https://openalex.org/W2043834751","https://openalex.org/W2008764415"],"abstract_inverted_index":{"Digital":[0],"signal":[1],"processors":[2],"(DSPs)":[3],"commonly":[4],"employ":[5],"indirect":[6],"addressing":[7,44],"mode":[8],"using":[9],"an":[10,36,58,94],"address":[11],"register":[12,38],"(AR).":[13],"For":[14,46],"such":[15,57],"DSPs,":[16,35],"reduction":[17,48],"in":[18,27,42,49,64,87],"overhead":[19,50,72],"codes":[20],"over":[21],"memory":[22,53],"access":[23],"is":[24,40,62,91,97,116],"quite":[25],"important":[26],"order":[28,68],"to":[29,69,92,117],"generate":[30],"efficient":[31],"codes.":[32],"In":[33,67],"some":[34],"index":[37],"(IX)":[39],"provided":[41],"the":[43,52,71,81,88,104,119],"mode.":[45],"further":[47],"codes,":[51,73],"allocation":[54],"method":[55,111],"utilizing":[56],"IX":[59],"update":[60],"operation":[61],"considered":[63],"this":[65],"paper.":[66],"reduce":[70],"two":[74],"algorithms":[75],"are":[76],"applied.":[77],"The":[78,101],"purpose":[79,102],"of":[80,103,122],"first":[82],"algorithm":[83,106],"(4.1":[84],"Lower":[85],"variance":[86],"AR":[89,114,123],"modification)":[90],"obtain":[93],"allocation,":[95],"which":[96],"convenient":[98],"for":[99],"IX.":[100,125],"second":[105],"(4.2":[107],"Memory":[108],"a":[109],"location":[110],"with":[112],"less":[113],"loads)":[115],"make":[118],"best":[120],"use":[121],"and":[124]},"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}