{"id":"https://openalex.org/W1548219056","doi":"https://doi.org/10.1109/apccas.2002.1114926","title":"A high-level synthesis method for simultaneous placement and scheduling considering data communication delay","display_name":"A high-level synthesis method for simultaneous placement and scheduling considering data communication delay","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W1548219056","doi":"https://doi.org/10.1109/apccas.2002.1114926","mag":"1548219056"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2002.1114926","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1114926","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065652494","display_name":"Koichiro Ito","orcid":"https://orcid.org/0000-0002-2167-582X"},"institutions":[{"id":"https://openalex.org/I72253084","display_name":"Saitama University","ror":"https://ror.org/02evnh647","country_code":"JP","type":"education","lineage":["https://openalex.org/I72253084"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"K. Ito","raw_affiliation_strings":["Department Electrical Electrical Systems, Saitama University, Saitama, Saitama, Japan","Dept. Elec. Elect. Syst., Saitama Univ., Japan"],"affiliations":[{"raw_affiliation_string":"Department Electrical Electrical Systems, Saitama University, Saitama, Saitama, Japan","institution_ids":["https://openalex.org/I72253084"]},{"raw_affiliation_string":"Dept. Elec. Elect. Syst., Saitama Univ., Japan","institution_ids":["https://openalex.org/I72253084"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109118395","display_name":"Daiki Suzuki","orcid":null},"institutions":[{"id":"https://openalex.org/I72253084","display_name":"Saitama University","ror":"https://ror.org/02evnh647","country_code":"JP","type":"education","lineage":["https://openalex.org/I72253084"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"D. Suzuki","raw_affiliation_strings":["Department Electrical Electrical Systems, Saitama University, Saitama, Saitama, Japan","Dept. Elec. Elect. Syst., Saitama Univ., Japan"],"affiliations":[{"raw_affiliation_string":"Department Electrical Electrical Systems, Saitama University, Saitama, Saitama, Japan","institution_ids":["https://openalex.org/I72253084"]},{"raw_affiliation_string":"Dept. Elec. Elect. Syst., Saitama Univ., Japan","institution_ids":["https://openalex.org/I72253084"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5065652494"],"corresponding_institution_ids":["https://openalex.org/I72253084"],"apc_list":null,"apc_paid":null,"fwci":1.1057,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.74582479,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"149","last_page":"154"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7461792230606079},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7049916982650757},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6227710247039795},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5752855539321899},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.5501233339309692},{"id":"https://openalex.org/keywords/elmore-delay","display_name":"Elmore delay","score":0.5007727146148682},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4935392141342163},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.4903161823749542},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.46636685729026794},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.4581765830516815},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3342706263065338},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.29068896174430847},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.2596527338027954},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.2196732759475708},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19169211387634277},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1309906244277954}],"concepts":[{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7461792230606079},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7049916982650757},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6227710247039795},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5752855539321899},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.5501233339309692},{"id":"https://openalex.org/C84434228","wikidata":"https://www.wikidata.org/wiki/Q4531332","display_name":"Elmore delay","level":4,"score":0.5007727146148682},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4935392141342163},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.4903161823749542},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.46636685729026794},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.4581765830516815},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3342706263065338},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.29068896174430847},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2596527338027954},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.2196732759475708},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19169211387634277},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1309906244277954},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2002.1114926","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1114926","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2096691549","https://openalex.org/W2121036163","https://openalex.org/W2134354173","https://openalex.org/W2158664566","https://openalex.org/W2166829915"],"related_works":["https://openalex.org/W2114232017","https://openalex.org/W2020200124","https://openalex.org/W1691923927","https://openalex.org/W2380365775","https://openalex.org/W2182628752","https://openalex.org/W4211170193","https://openalex.org/W4238419543","https://openalex.org/W1548219056","https://openalex.org/W2129468521","https://openalex.org/W1516835811"],"abstract_inverted_index":{"With":[0,108],"the":[1,21,34,44,51,55,115,125],"development":[2],"of":[3,40,105,127],"deep":[4],"submicron":[5],"technology,":[6],"wire":[7,41,69,111],"delay":[8,42,70,112],"on":[9,114],"an":[10],"LSI":[11],"chip":[12],"is":[13,28,47,117],"becoming":[14],"relatively":[15],"larger":[16],"than":[17],"gate":[18],"delay.":[19],"In":[20,63,83],"conventional":[22],"VLSI":[23],"design":[24,27,46],"flow,":[25],"high-level":[26,45,81],"usually":[29],"performed":[30],"without":[31],"information":[32],"about":[33],"physical":[35,56],"layout":[36,57],"design.":[37,82],"The":[38],"estimation":[39],"during":[43,124],"not":[48,60],"accurate":[49],"and":[50,74,103,120],"final":[52],"performance,":[53],"after":[54],"design,":[58],"might":[59],"satisfy":[61],"requirements.":[62],"order":[64],"to":[65,90],"overcome":[66],"this":[67,84,109],"problem,":[68],"determined":[71],"by":[72,100],"placement":[73,104,116],"routing":[75],"must":[76],"be":[77,122],"considered":[78,119],"even":[79],"in":[80],"paper":[85],"we":[86],"propose":[87],"a":[88,96],"method":[89],"achieve":[91],"high":[92],"speed":[93],"processing":[94,98],"for":[95],"given":[97],"algorithm":[99],"performing":[101],"scheduling":[102,126],"operations":[106],"simultaneously.":[107],"method,":[110],"based":[113],"precisely":[118],"may":[121],"minimized":[123],"operations.":[128]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}