{"id":"https://openalex.org/W1746001235","doi":"https://doi.org/10.1109/apccas.2002.1114907","title":"Datapath oriented codesign method of application specific DSPs using retargetable compiler","display_name":"Datapath oriented codesign method of application specific DSPs using retargetable compiler","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W1746001235","doi":"https://doi.org/10.1109/apccas.2002.1114907","mag":"1746001235"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2002.1114907","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1114907","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000088287","display_name":"Nagisa Ishiura","orcid":null},"institutions":[{"id":"https://openalex.org/I206011266","display_name":"Kwansei Gakuin University","ror":"https://ror.org/02qf2tx24","country_code":"JP","type":"education","lineage":["https://openalex.org/I206011266"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"N. Ishiura","raw_affiliation_strings":["School of Science and Technology, Kwansei Gakuin University, Sanda, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"School of Science and Technology, Kwansei Gakuin University, Sanda, Hyogo, Japan","institution_ids":["https://openalex.org/I206011266"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039191716","display_name":"Watanabe Tatsuo","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"T. Watanabe","raw_affiliation_strings":["Integrated Circuits Development Group, SHARP Corporation, Nara, Japan"],"affiliations":[{"raw_affiliation_string":"Integrated Circuits Development Group, SHARP Corporation, Nara, Japan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5000088287"],"corresponding_institution_ids":["https://openalex.org/I206011266"],"apc_list":null,"apc_paid":null,"fwci":0.5124,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.52732871,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"55","last_page":"58"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9791712164878845},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.8313019871711731},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8073850274085999},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.6618787050247192},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.6223772764205933},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5461429953575134},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.535460889339447},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5232017040252686},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4648731052875519},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.44768384099006653},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.437541127204895},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35414576530456543},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.34292665123939514},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.33756983280181885},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14886274933815002}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9791712164878845},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.8313019871711731},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8073850274085999},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.6618787050247192},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.6223772764205933},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5461429953575134},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.535460889339447},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5232017040252686},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4648731052875519},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.44768384099006653},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.437541127204895},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35414576530456543},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.34292665123939514},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.33756983280181885},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14886274933815002},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2002.1114907","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2002.1114907","pdf_url":null,"source":{"id":"https://openalex.org/S4306417752","display_name":"Asia Pacific Conference on Circuits and Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia-Pacific Conference on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320320879","display_name":"Deutsche Forschungsgemeinschaft","ror":"https://ror.org/018mejw64"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W993824660","https://openalex.org/W1591546244","https://openalex.org/W1777501891","https://openalex.org/W2105211230","https://openalex.org/W2109607425","https://openalex.org/W2170381446","https://openalex.org/W6625997588","https://openalex.org/W6635354450"],"related_works":["https://openalex.org/W2367718038","https://openalex.org/W650988184","https://openalex.org/W2162921448","https://openalex.org/W2162410319","https://openalex.org/W2100984465","https://openalex.org/W2137356287","https://openalex.org/W4321184925","https://openalex.org/W4247613350","https://openalex.org/W2129565950","https://openalex.org/W4281693886"],"abstract_inverted_index":{"Proposes":[0],"a":[1,30,43,53],"\"datapath":[2],"oriented\"":[3],"codesign":[4],"methodology,":[5],"which":[6],"uses":[7],"datapath":[8,32],"configurations":[9],"and":[10,23,29,42,62,66],"horizontal":[11,44],"codes,":[12],"instead":[13],"of":[14,37,72],"instruction":[15],"set":[16],"specifications":[17],"as":[18],"an":[19,26],"interface":[20],"between":[21],"hardware":[22],"software.":[24],"Given":[25],"application":[27,73],"program":[28],"DSP":[31,39,49],"configuration,":[33],"the":[34,38,48,59,69],"control":[35,47],"part":[36],"is":[40,50],"synthesized":[41],"code":[45,63],"to":[46],"generated":[51],"by":[52],"retargetable":[54],"compiler.":[55],"This":[56],"method":[57],"simplifies":[58],"processor":[60],"synthesis":[61],"generation":[64],"tasks":[65],"will":[67],"expedite":[68],"design":[70],"automation":[71],"specific":[74],"DSPs":[75],"with":[76],"sophisticated":[77],"datapaths.":[78]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
