{"id":"https://openalex.org/W4237601343","doi":"https://doi.org/10.1109/ancs.2013.6665198","title":"Asymmetric scaling on network packet processors in the dark silicon era","display_name":"Asymmetric scaling on network packet processors in the dark silicon era","publication_year":2013,"publication_date":"2013-10-01","ids":{"openalex":"https://openalex.org/W4237601343","doi":"https://doi.org/10.1109/ancs.2013.6665198"},"language":"en","primary_location":{"id":"doi:10.1109/ancs.2013.6665198","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ancs.2013.6665198","pdf_url":null,"source":{"id":"https://openalex.org/S4306417706","display_name":"Architectures for Networking and Communications Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Architectures for Networking and Communications Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081698640","display_name":"Sourav Roy","orcid":"https://orcid.org/0000-0002-3927-571X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Sourav Roy","raw_affiliation_strings":["Freescale Semiconductor Inc"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor Inc","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103771344","display_name":"Xiaomin Lu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Xiaomin Lu","raw_affiliation_strings":["Freescale Semiconductor Inc"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor Inc","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080104911","display_name":"Edmund Gieske","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Edmund Gieske","raw_affiliation_strings":["Freescale Semiconductor Inc"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor Inc","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100681631","display_name":"Peng Yang","orcid":"https://orcid.org/0000-0002-0063-3102"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Peng Yang","raw_affiliation_strings":["Freescale Semiconductor Inc"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor Inc","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035704908","display_name":"Jim Holt","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jim Holt","raw_affiliation_strings":["Freescale Semiconductor Inc"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor Inc","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4074,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.67113784,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"157","last_page":"167"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.6949412822723389},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.693946897983551},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.6172118782997131},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.5840677618980408},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.5731276273727417},{"id":"https://openalex.org/keywords/frequency-scaling","display_name":"Frequency scaling","score":0.5446774363517761},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5183571577072144},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.47083520889282227},{"id":"https://openalex.org/keywords/network-processor","display_name":"Network processor","score":0.45012354850769043},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4490613639354706},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3285912871360779},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2405187487602234},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.22107890248298645},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11679750680923462},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10873344540596008},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09197333455085754}],"concepts":[{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.6949412822723389},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.693946897983551},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.6172118782997131},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.5840677618980408},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.5731276273727417},{"id":"https://openalex.org/C157742956","wikidata":"https://www.wikidata.org/wiki/Q3237776","display_name":"Frequency scaling","level":3,"score":0.5446774363517761},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5183571577072144},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.47083520889282227},{"id":"https://openalex.org/C74366991","wikidata":"https://www.wikidata.org/wiki/Q2755335","display_name":"Network processor","level":3,"score":0.45012354850769043},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4490613639354706},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3285912871360779},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2405187487602234},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.22107890248298645},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11679750680923462},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10873344540596008},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09197333455085754},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ancs.2013.6665198","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ancs.2013.6665198","pdf_url":null,"source":{"id":"https://openalex.org/S4306417706","display_name":"Architectures for Networking and Communications Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Architectures for Networking and Communications Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7900000214576721}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1516402079","https://openalex.org/W1998525920","https://openalex.org/W2003313945","https://openalex.org/W2006312753","https://openalex.org/W2015338849","https://openalex.org/W2046574526","https://openalex.org/W2064866989","https://openalex.org/W2089155985","https://openalex.org/W2105186402","https://openalex.org/W2116578804","https://openalex.org/W2128188789","https://openalex.org/W2133979350","https://openalex.org/W2140130374","https://openalex.org/W2140761742","https://openalex.org/W2145376025","https://openalex.org/W2153236055","https://openalex.org/W2157211828","https://openalex.org/W2207094710","https://openalex.org/W3142147837","https://openalex.org/W4236062646","https://openalex.org/W4253401904","https://openalex.org/W6651700774","https://openalex.org/W6681001561","https://openalex.org/W6681352259","https://openalex.org/W6685464560","https://openalex.org/W7046116536"],"related_works":["https://openalex.org/W2154351074","https://openalex.org/W2151223307","https://openalex.org/W1547865754","https://openalex.org/W2276000909","https://openalex.org/W2023400509","https://openalex.org/W2332054630","https://openalex.org/W2590100594","https://openalex.org/W2154169726","https://openalex.org/W2131429702","https://openalex.org/W2898122376"],"abstract_inverted_index":{"This":[0],"paper":[1],"introduces":[2],"a":[3,39,99,116,152,173],"new":[4],"architectural":[5],"technique":[6],"called":[7],"asymmetric":[8,28,64],"scaling":[9,65,91],"on":[10,98],"heterogeneous":[11],"multi-core":[12],"network":[13,100,111],"processor":[14,112,180],"architectures":[15],"to":[16,87,142],"mitigate":[17],"the":[18,30,43,68,72,75,95,105,109,144,177],"problem":[19],"of":[20,32,45,71,120,130,147],"dark":[21],"silicon":[22],"in":[23],"future":[24],"process":[25,50,80],"technologies.":[26],"In":[27],"scaling,":[29,63],"number":[31,44],"low":[33,131,148,178],"power":[34,69,132,145,149,179],"cores":[35,48,123,163],"is":[36],"increased":[37],"at":[38,74],"higher":[40],"rate":[41],"than":[42],"high":[46,121],"performance":[47,122],"over":[49],"generations.":[51],"Using":[52,151],"an":[53,125],"analytical":[54],"model":[55],"we":[56,107,157],"show":[57,158],"that":[58,114,138,159],"coupled":[59],"with":[60,94,124,164],"fixed":[61],"voltage-frequency":[62],"can":[66,139],"maintain":[67],"density":[70,146],"chip":[73],"same":[76],"level":[77],"for":[78,176],"several":[79,136],"generations,":[81],"while":[82],"increasing":[83],"computational":[84],"capabilities":[85],"according":[86],"Dennardian":[88],"scaling.":[89],"Asymmetric":[90],"aligns":[92],"nicely":[93],"application":[96],"characteristics":[97],"packet":[101,127,154],"processor.":[102],"To":[103],"illustrate":[104],"concept,":[106],"discuss":[108,135],"Layerscape":[110],"architecture":[113],"incorporates":[115],"general":[117],"purpose":[118],"layer":[119,129],"accelerated":[126],"processing":[128],"cores.":[133,150],"We":[134],"techniques":[137],"be":[140],"applied":[141],"reduce":[143],"representative":[153],"forwarding":[155],"workload,":[156],"shallow-pipeline,":[160],"dual-issue,":[161],"in-order":[162],"appropriate":[165],"hardware":[166],"acceleration":[167],"and":[168],"limited":[169],"on-chip":[170],"memory":[171],"are":[172],"good":[174],"choice":[175],"layer.":[181]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}