{"id":"https://openalex.org/W2506885233","doi":"https://doi.org/10.1109/aiccsa.2015.7507197","title":"Area and delay aware approaches for realizing multi-operand addition on FPGAs using two-operand adders","display_name":"Area and delay aware approaches for realizing multi-operand addition on FPGAs using two-operand adders","publication_year":2015,"publication_date":"2015-11-01","ids":{"openalex":"https://openalex.org/W2506885233","doi":"https://doi.org/10.1109/aiccsa.2015.7507197","mag":"2506885233"},"language":"en","primary_location":{"id":"doi:10.1109/aiccsa.2015.7507197","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aiccsa.2015.7507197","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE/ACS 12th International Conference of Computer Systems and Applications (AICCSA)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034249267","display_name":"Noureddine Chabini","orcid":null},"institutions":[{"id":"https://openalex.org/I51768193","display_name":"Royal Military College of Canada","ror":"https://ror.org/04yr71909","country_code":"CA","type":"education","lineage":["https://openalex.org/I51768193"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Noureddine Chabini","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Royal Military College of Canada, Kingston, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Royal Military College of Canada, Kingston, ON, Canada","institution_ids":["https://openalex.org/I51768193"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059874562","display_name":"Sa\u00efd Belkouch","orcid":null},"institutions":[{"id":"https://openalex.org/I119856527","display_name":"Cadi Ayyad University","ror":"https://ror.org/04xf6nm78","country_code":"MA","type":"education","lineage":["https://openalex.org/I119856527"]}],"countries":["MA"],"is_corresponding":false,"raw_author_name":"Said Belkouch","raw_affiliation_strings":["National School of Applied Sciences, University of Cadi Ayyad, Marrakech, Morocco"],"affiliations":[{"raw_affiliation_string":"National School of Applied Sciences, University of Cadi Ayyad, Marrakech, Morocco","institution_ids":["https://openalex.org/I119856527"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5034249267"],"corresponding_institution_ids":["https://openalex.org/I51768193"],"apc_list":null,"apc_paid":null,"fwci":0.646,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.72470037,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.9930005073547363},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8498721122741699},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.713428258895874},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6752152442932129},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6111487746238708},{"id":"https://openalex.org/keywords/focus","display_name":"Focus (optics)","score":0.5761260986328125},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.34198927879333496},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.19908800721168518},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.15694662928581238},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06281015276908875}],"concepts":[{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.9930005073547363},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8498721122741699},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.713428258895874},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6752152442932129},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6111487746238708},{"id":"https://openalex.org/C192209626","wikidata":"https://www.wikidata.org/wiki/Q190909","display_name":"Focus (optics)","level":2,"score":0.5761260986328125},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.34198927879333496},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.19908800721168518},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15694662928581238},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06281015276908875},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aiccsa.2015.7507197","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aiccsa.2015.7507197","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE/ACS 12th International Conference of Computer Systems and Applications (AICCSA)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Responsible consumption and production","score":0.5,"id":"https://metadata.un.org/sdg/12"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W201024842","https://openalex.org/W1968143987","https://openalex.org/W2033102853","https://openalex.org/W2036075346","https://openalex.org/W2088602259","https://openalex.org/W2144014713","https://openalex.org/W2798566347"],"related_works":["https://openalex.org/W2967107136","https://openalex.org/W2072220574","https://openalex.org/W4285082868","https://openalex.org/W2162004439","https://openalex.org/W2558076308","https://openalex.org/W4317402486","https://openalex.org/W2120552212","https://openalex.org/W2013839957","https://openalex.org/W3196607417","https://openalex.org/W2090865818"],"abstract_inverted_index":{"Multi-operand":[0],"addition":[1,18],"is":[2],"found":[3],"in":[4],"many":[5],"real-life":[6],"applications.":[7],"In":[8],"this":[9],"paper,":[10],"we":[11],"propose":[12],"two":[13],"approaches":[14,30],"for":[15],"realizing":[16],"multi-operand":[17],"using":[19],"two-operand":[20],"adders":[21],"on":[22,45],"Field":[23],"Programmed":[24],"Gate":[25],"Arrays":[26],"(FPGAs).":[27],"The":[28],"proposed":[29],"reduce":[31],"the":[32,35,46,49],"area":[33],"of":[34,52],"final":[36],"implementation":[37],"while":[38],"reducing":[39],"its":[40],"propagation":[41],"delay.":[42],"We":[43],"focus":[44],"case":[47],"where":[48],"operands":[50],"are":[51],"different":[53],"sizes.":[54]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2017,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
