{"id":"https://openalex.org/W2135114615","doi":"https://doi.org/10.1109/aiccsa.2005.1387021","title":"Acyclic circuit partitioning for path delay fault emulation","display_name":"Acyclic circuit partitioning for path delay fault emulation","publication_year":2005,"publication_date":"2005-04-01","ids":{"openalex":"https://openalex.org/W2135114615","doi":"https://doi.org/10.1109/aiccsa.2005.1387021","mag":"2135114615"},"language":"en","primary_location":{"id":"doi:10.1109/aiccsa.2005.1387021","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aiccsa.2005.1387021","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 3rd ACS/IEEE International Conference onComputer Systems and Applications, 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016021239","display_name":"Fatih Kocan","orcid":null},"institutions":[{"id":"https://openalex.org/I178169726","display_name":"Southern Methodist University","ror":"https://ror.org/042tdr378","country_code":"US","type":"education","lineage":["https://openalex.org/I178169726"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"F. Kocan","raw_affiliation_strings":["Computer Science and Engineering, Southern Methodist University, USA","Computer Science and Engineering, Southern Methodist University, Dallas, TX, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Computer Science and Engineering, Southern Methodist University, USA","institution_ids":["https://openalex.org/I178169726"]},{"raw_affiliation_string":"Computer Science and Engineering, Southern Methodist University, Dallas, TX, USA#TAB#","institution_ids":["https://openalex.org/I178169726"]}]},{"author_position":"last","author":{"id":null,"display_name":"M.H. Gunes","orcid":null},"institutions":[{"id":"https://openalex.org/I178169726","display_name":"Southern Methodist University","ror":"https://ror.org/042tdr378","country_code":"US","type":"education","lineage":["https://openalex.org/I178169726"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.H. Gunes","raw_affiliation_strings":["Computer Science and Engineering, Southern Methodist University, USA","Computer Science and Engineering, Southern Methodist University, Dallas, TX, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Computer Science and Engineering, Southern Methodist University, USA","institution_ids":["https://openalex.org/I178169726"]},{"raw_affiliation_string":"Computer Science and Engineering, Southern Methodist University, Dallas, TX, USA#TAB#","institution_ids":["https://openalex.org/I178169726"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5016021239"],"corresponding_institution_ids":["https://openalex.org/I178169726"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.19781735,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"76","last_page":"80"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.7921230792999268},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.7769660949707031},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.7409460544586182},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6507848501205444},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6438789963722229},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5198945999145508},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4918234348297119},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.35022756457328796},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.24743756651878357},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.11686274409294128},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.06369924545288086}],"concepts":[{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.7921230792999268},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.7769660949707031},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.7409460544586182},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6507848501205444},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6438789963722229},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5198945999145508},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4918234348297119},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.35022756457328796},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.24743756651878357},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.11686274409294128},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.06369924545288086},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aiccsa.2005.1387021","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aiccsa.2005.1387021","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 3rd ACS/IEEE International Conference onComputer Systems and Applications, 2005.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W13277579","https://openalex.org/W2086629796","https://openalex.org/W2118606639","https://openalex.org/W2127569460","https://openalex.org/W2147071478","https://openalex.org/W2161675672","https://openalex.org/W6600530048","https://openalex.org/W6684113476"],"related_works":["https://openalex.org/W2154523322","https://openalex.org/W2083200807","https://openalex.org/W1603137082","https://openalex.org/W2364195017","https://openalex.org/W2355430452","https://openalex.org/W2049983405","https://openalex.org/W2392315374","https://openalex.org/W1951195060","https://openalex.org/W2351776620","https://openalex.org/W2352195574"],"abstract_inverted_index":{"Summary":[0],"form":[1],"only":[2],"given.":[3],"Acyclic":[4],"partitioning":[5,37,68,72],"of":[6,104,107],"VLSI":[7],"circuits":[8],"is":[9],"studied":[10],"under":[11],"area/delay,":[12],"1-0":[13],"size":[14],"and":[15,57,98,111],"communication":[16],"constraints.":[17],"In":[18],"this":[19],"paper,":[20],"we":[21],"define":[22],"the":[23,45,71,81,85,89,95,105],"path-delay-fault":[24],"emulation":[25],"problem":[26],"which":[27,87],"adds":[28],"a":[29,51],"new":[30],"constraint,":[31,35],"viz.":[32],"path":[33,75,90],"count":[34,76,91],"to":[36,43,84],"problem.":[38,46],"We":[39,93],"present":[40],"two":[41],"algorithms":[42],"solve":[44],"The":[47,62],"first":[48,82,96],"algorithm":[49,73,83,97],"decomposes":[50],"circuit":[52],"into":[53,60],"entirely-fanout-free":[54],"cones":[55],"(EFFC),":[56],"clusters":[58],"them":[59],"partitions.":[61],"second":[63],"one":[64],"finds":[65],"an":[66],"intermediate":[67],"solution":[69],"with":[70],"ignoring":[74],"constraint.":[77,92],"Later,":[78],"it":[79],"applies":[80],"partitions":[86],"violate":[88],"implemented":[94],"measured":[99],"its":[100],"efficiency":[101],"in":[102],"terms":[103],"number":[106],"resulting":[108],"partitions,":[109],"cut-cost,":[110],"time":[112],"cost":[113],"for":[114],"ISCAS85":[115],"benchmarks.":[116]},"counts_by_year":[],"updated_date":"2026-03-25T23:56:10.502304","created_date":"2025-10-10T00:00:00"}
