{"id":"https://openalex.org/W4414500269","doi":"https://doi.org/10.1109/aicas64808.2025.11173138","title":"Design of an Analog Integrated Circuit Solving the Two-Armed Bandit Problem in 180-nm CMOS","display_name":"Design of an Analog Integrated Circuit Solving the Two-Armed Bandit Problem in 180-nm CMOS","publication_year":2025,"publication_date":"2025-04-28","ids":{"openalex":"https://openalex.org/W4414500269","doi":"https://doi.org/10.1109/aicas64808.2025.11173138"},"language":"en","primary_location":{"id":"doi:10.1109/aicas64808.2025.11173138","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aicas64808.2025.11173138","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE 7th International Conference on Artificial Intelligence Circuits and Systems (AICAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102395561","display_name":"Kohei Mori","orcid":null},"institutions":[{"id":"https://openalex.org/I16656306","display_name":"Meiji University","ror":"https://ror.org/02rqvrp93","country_code":"JP","type":"education","lineage":["https://openalex.org/I16656306"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Kohei Mori","raw_affiliation_strings":["Meiji University,Graduate School of Science and Technology,Japan"],"affiliations":[{"raw_affiliation_string":"Meiji University,Graduate School of Science and Technology,Japan","institution_ids":["https://openalex.org/I16656306"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103731117","display_name":"Kazuyuki Wada","orcid":null},"institutions":[{"id":"https://openalex.org/I16656306","display_name":"Meiji University","ror":"https://ror.org/02rqvrp93","country_code":"JP","type":"education","lineage":["https://openalex.org/I16656306"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kazuyuki Wada","raw_affiliation_strings":["Meiji University,Graduate School of Science and Technology,Japan"],"affiliations":[{"raw_affiliation_string":"Meiji University,Graduate School of Science and Technology,Japan","institution_ids":["https://openalex.org/I16656306"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055164128","display_name":"Kawori Sekine","orcid":"https://orcid.org/0000-0003-4166-0796"},"institutions":[{"id":"https://openalex.org/I16656306","display_name":"Meiji University","ror":"https://ror.org/02rqvrp93","country_code":"JP","type":"education","lineage":["https://openalex.org/I16656306"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kawori Sekine","raw_affiliation_strings":["Meiji University,Graduate School of Science and Technology,Japan"],"affiliations":[{"raw_affiliation_string":"Meiji University,Graduate School of Science and Technology,Japan","institution_ids":["https://openalex.org/I16656306"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087411720","display_name":"Shinsuke Hara","orcid":null},"institutions":[{"id":"https://openalex.org/I90023481","display_name":"National Institute of Information and Communications Technology","ror":"https://ror.org/016bgq349","country_code":"JP","type":"facility","lineage":["https://openalex.org/I90023481"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shinsuke Hara","raw_affiliation_strings":["National Institute of Information and Communications Technology,Japan"],"affiliations":[{"raw_affiliation_string":"National Institute of Information and Communications Technology,Japan","institution_ids":["https://openalex.org/I90023481"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000510993","display_name":"Satoru Tanoi","orcid":"https://orcid.org/0000-0001-9173-8569"},"institutions":[{"id":"https://openalex.org/I90023481","display_name":"National Institute of Information and Communications Technology","ror":"https://ror.org/016bgq349","country_code":"JP","type":"facility","lineage":["https://openalex.org/I90023481"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Satoru Tanoi","raw_affiliation_strings":["National Institute of Information and Communications Technology,Japan"],"affiliations":[{"raw_affiliation_string":"National Institute of Information and Communications Technology,Japan","institution_ids":["https://openalex.org/I90023481"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5015167716","display_name":"Akifumi Kasamatsu","orcid":"https://orcid.org/0000-0002-2217-6272"},"institutions":[{"id":"https://openalex.org/I90023481","display_name":"National Institute of Information and Communications Technology","ror":"https://ror.org/016bgq349","country_code":"JP","type":"facility","lineage":["https://openalex.org/I90023481"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Akifumi Kasamatsu","raw_affiliation_strings":["National Institute of Information and Communications Technology,Japan"],"affiliations":[{"raw_affiliation_string":"National Institute of Information and Communications Technology,Japan","institution_ids":["https://openalex.org/I90023481"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5102395561"],"corresponding_institution_ids":["https://openalex.org/I16656306"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.27634643,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9918000102043152,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9918000102043152,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9861000180244446,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.9674000144004822,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5881999731063843},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.5842999815940857},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.5609999895095825},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.5055999755859375},{"id":"https://openalex.org/keywords/simple","display_name":"Simple (philosophy)","score":0.49810001254081726},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.4970000088214874},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.39910000562667847},{"id":"https://openalex.org/keywords/discrete-circuit","display_name":"Discrete circuit","score":0.38119998574256897},{"id":"https://openalex.org/keywords/analog-multiplier","display_name":"Analog multiplier","score":0.3797999918460846}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6021999716758728},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5881999731063843},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.5842999815940857},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5842000246047974},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.5609999895095825},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.5055999755859375},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.49810001254081726},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.4970000088214874},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.39910000562667847},{"id":"https://openalex.org/C188058453","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Discrete circuit","level":4,"score":0.38119998574256897},{"id":"https://openalex.org/C98142538","wikidata":"https://www.wikidata.org/wiki/Q485005","display_name":"Analog multiplier","level":4,"score":0.3797999918460846},{"id":"https://openalex.org/C171065743","wikidata":"https://www.wikidata.org/wiki/Q5279089","display_name":"Diode-or circuit","level":5,"score":0.37619999051094055},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.3758000135421753},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.3540000021457672},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.34880000352859497},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.3366999924182892},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3149000108242035},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.3037000000476837},{"id":"https://openalex.org/C90201813","wikidata":"https://www.wikidata.org/wiki/Q202957","display_name":"Schmitt trigger","level":3,"score":0.29820001125335693},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.2946999967098236},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.29409998655319214},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.2935999929904938},{"id":"https://openalex.org/C2780167933","wikidata":"https://www.wikidata.org/wiki/Q1550652","display_name":"Pulse (music)","level":3,"score":0.28200000524520874},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.2703999876976013},{"id":"https://openalex.org/C52773712","wikidata":"https://www.wikidata.org/wiki/Q175022","display_name":"Digital signal","level":3,"score":0.2680000066757202},{"id":"https://openalex.org/C113089479","wikidata":"https://www.wikidata.org/wiki/Q210729","display_name":"Electrical element","level":2,"score":0.25110000371932983},{"id":"https://openalex.org/C194571574","wikidata":"https://www.wikidata.org/wiki/Q2251187","display_name":"Linear circuit","level":4,"score":0.25060001015663147},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25049999356269836},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.2500999867916107}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aicas64808.2025.11173138","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aicas64808.2025.11173138","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE 7th International Conference on Artificial Intelligence Circuits and Systems (AICAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1968632892","https://openalex.org/W2963699095","https://openalex.org/W2971854266","https://openalex.org/W2973231024","https://openalex.org/W4206522438","https://openalex.org/W4287009381"],"related_works":[],"abstract_inverted_index":{"A":[0,78],"design":[1,64],"of":[2,19,27,43,53,58,98,111],"an":[3,44,102],"analog":[4],"integrated":[5],"circuit":[6,47,81,99,118],"for":[7,119],"solving":[8,120],"the":[9,16,20,25,55,67,109,112,121],"two-armed":[10],"bandit":[11,22,122],"(2AB)":[12],"problem,":[13],"which":[14],"is":[15,30,38,66,82,86,94],"simplest":[17],"version":[18],"multi-armed":[21],"problem":[23,123],"in":[24,128],"fields":[26],"machine":[28],"learning,":[29],"presented":[31],"using":[32,48,101],"a":[33,41,95,115,129],"180-nm":[34],"standard":[35],"CMOS.":[36],"It":[37],"considered":[39],"as":[40,114],"candidate":[42],"ultra-high":[45],"speed":[46,56],"photonic":[49],"chaos":[50],"signal":[51],"because":[52],"relaxing":[54],"limitation":[57],"digital":[59],"logic":[60],"circuits.":[61],"In":[62],"this":[63,93],"it":[65,107],"most":[68],"important":[69],"to":[70,88],"perform":[71],"system":[72,90,113],"level":[73],"operation":[74,100,110],"without":[75],"any":[76],"error.":[77],"pulse":[79],"generation":[80],"introduced":[83],"and":[84],"timing":[85],"adjusted":[87],"minimize":[89],"errors.":[91],"Although":[92],"simple":[96],"verification":[97],"easily":[103],"accessible":[104],"measurement":[105],"system,":[106],"demonstrates":[108],"whole.":[116],"The":[117],"operated":[124],"at":[125],"2.0":[126],"GHz":[127],"measurement.":[130]},"counts_by_year":[],"updated_date":"2026-03-07T16:01:11.037858","created_date":"2025-10-10T00:00:00"}
