{"id":"https://openalex.org/W4400811286","doi":"https://doi.org/10.1109/aicas59952.2024.10595855","title":"Deploying Artificial Intelligence in Design Verification to Accelerate IP/SoC Sign-off with Zero Escape","display_name":"Deploying Artificial Intelligence in Design Verification to Accelerate IP/SoC Sign-off with Zero Escape","publication_year":2024,"publication_date":"2024-04-22","ids":{"openalex":"https://openalex.org/W4400811286","doi":"https://doi.org/10.1109/aicas59952.2024.10595855"},"language":"en","primary_location":{"id":"doi:10.1109/aicas59952.2024.10595855","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aicas59952.2024.10595855","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009742420","display_name":"Surajit Bhattacherjee","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Surajit Bhattacherjee","raw_affiliation_strings":["Birla Institute of Technology & Science, Pilani, K.K. Birla,Dept. of Electrical & Electronics Engg.,Goa,India"],"affiliations":[{"raw_affiliation_string":"Birla Institute of Technology & Science, Pilani, K.K. Birla,Dept. of Electrical & Electronics Engg.,Goa,India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113296037","display_name":"Daksh Shah","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Daksh Shah","raw_affiliation_strings":["Birla Institute of Technology & Science, Pilani, K.K. Birla,Dept. of Electrical & Electronics Engg.,Goa,India"],"affiliations":[{"raw_affiliation_string":"Birla Institute of Technology & Science, Pilani, K.K. Birla,Dept. of Electrical & Electronics Engg.,Goa,India","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101520559","display_name":"Dipankar Pal","orcid":"https://orcid.org/0000-0001-8514-0077"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Dipankar Pal","raw_affiliation_strings":["Birla Institute of Technology & Science, Pilani, K.K. Birla,Dept. of Electrical & Electronics Engg.,Goa,India"],"affiliations":[{"raw_affiliation_string":"Birla Institute of Technology & Science, Pilani, K.K. Birla,Dept. of Electrical & Electronics Engg.,Goa,India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5009742420"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.5186,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.60809086,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"477","last_page":"481"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9912999868392944,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6890549659729004},{"id":"https://openalex.org/keywords/sign","display_name":"Sign (mathematics)","score":0.5991496443748474},{"id":"https://openalex.org/keywords/zero","display_name":"Zero (linguistics)","score":0.5534871220588684},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5259756445884705},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37583979964256287},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07794728875160217}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6890549659729004},{"id":"https://openalex.org/C139676723","wikidata":"https://www.wikidata.org/wiki/Q1193832","display_name":"Sign (mathematics)","level":2,"score":0.5991496443748474},{"id":"https://openalex.org/C2780813799","wikidata":"https://www.wikidata.org/wiki/Q3274237","display_name":"Zero (linguistics)","level":2,"score":0.5534871220588684},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5259756445884705},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37583979964256287},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07794728875160217},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aicas59952.2024.10595855","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aicas59952.2024.10595855","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1416883001","https://openalex.org/W3122147473","https://openalex.org/W3155012083","https://openalex.org/W3214794276","https://openalex.org/W3216160593","https://openalex.org/W4205212523","https://openalex.org/W4214821660","https://openalex.org/W4232656078","https://openalex.org/W4313315800","https://openalex.org/W4360605000"],"related_works":["https://openalex.org/W2036806516","https://openalex.org/W1967394420","https://openalex.org/W2565425548","https://openalex.org/W2392009442","https://openalex.org/W13556768","https://openalex.org/W2100663632","https://openalex.org/W2154106283","https://openalex.org/W2912613323","https://openalex.org/W2031621863","https://openalex.org/W2353292666"],"abstract_inverted_index":{"Design":[0,107],"verification":[1,16,47,137],"is":[2,53],"a":[3,72,85,127,135],"bottleneck":[4],"in":[5,19,79],"development":[6],"of":[7,34,84,105,120,130,134],"Intellectual":[8],"Property":[9],"(IP)":[10],"subsystems":[11],"and":[12,27,41,98],"System-on-Chip":[13],"(SoC).":[14],"State-of-art":[15],"processes":[17],"practiced":[18],"VLSI-industries":[20],"involve":[21],"methodologies":[22],"that":[23],"are":[24],"time-consuming,":[25],"effort-hungry":[26],"expensive.":[28],"They":[29],"also":[30,112],"have":[31],"high":[32,144],"possibilities":[33],"bug-escape":[35],"for":[36,132,150],"complex":[37,73],"memory-intensive,":[38],"computation-intensive,":[39],"mathematical":[40],"logical":[42],"design":[43],"modules":[44],"if":[45],"the":[46,50,106,121,148],"sign-off":[48,64],"at":[49],"IP-SoC":[51],"boundary":[52],"not":[54,100],"tightly":[55],"closed.":[56],"The":[57,124],"methodology":[58],"proposed":[59],"here":[60],"recommends":[61],"an":[62],"alternate":[63],"approach":[65],"through":[66],"Machine":[67],"Learning":[68],"(ML)":[69],"applications":[70],"on":[71],"design,":[74],"namely,":[75],"Temperature":[76],"Sensor":[77],"(TS)":[78],"Dual-In-line":[80],"Memory":[81,89],"Module":[82],"(DIMM)":[83],"Dynamic":[86],"Random":[87,95],"Access":[88],"(DRAM).":[90],"Factual":[91],"evidences":[92],"derived":[93],"from":[94],"Forest":[96],"classifier":[97],"regressor":[99],"only":[101],"confirm":[102],"behavioural":[103],"accuracy":[104,145],"Under":[108],"Test":[109],"(DUT)":[110],"but":[111],"portray":[113],"decision":[114],"trees":[115],"to":[116,139,153],"visualize":[117],"RTL":[118],"implementation":[119],"architectural":[122],"specification.":[123],"experiment":[125],"testifies":[126],"smooth":[128],"integration":[129],"ML-adaptor":[131],"analyses":[133],"formal":[136],"data-set":[138],"claim":[140],"faster":[141],"debug-ability":[142],"with":[143],"while":[146],"predicting":[147],"output":[149],"sample":[151],"stimuli":[152],"DUT.":[154]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2025-12-26T23:08:49.675405","created_date":"2025-10-10T00:00:00"}