{"id":"https://openalex.org/W4235163336","doi":"https://doi.org/10.1109/ahs.2018.8541481","title":"Hardware and Software Task Scheduling for ARM-FPGA Platforms","display_name":"Hardware and Software Task Scheduling for ARM-FPGA Platforms","publication_year":2018,"publication_date":"2018-08-01","ids":{"openalex":"https://openalex.org/W4235163336","doi":"https://doi.org/10.1109/ahs.2018.8541481"},"language":"en","primary_location":{"id":"doi:10.1109/ahs.2018.8541481","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ahs.2018.8541481","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083715561","display_name":"Alexander D\u00f6rflinger","orcid":null},"institutions":[{"id":"https://openalex.org/I94509681","display_name":"Technische Universit\u00e4t Braunschweig","ror":"https://ror.org/010nsgg66","country_code":"DE","type":"education","lineage":["https://openalex.org/I94509681"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Alexander Dorflinger","raw_affiliation_strings":["Institute of Computer and Network Engineering (IDA) TU Braunschweig, Braunschweig, Germany"],"affiliations":[{"raw_affiliation_string":"Institute of Computer and Network Engineering (IDA) TU Braunschweig, Braunschweig, Germany","institution_ids":["https://openalex.org/I94509681"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034024677","display_name":"Mark Albers","orcid":null},"institutions":[{"id":"https://openalex.org/I94509681","display_name":"Technische Universit\u00e4t Braunschweig","ror":"https://ror.org/010nsgg66","country_code":"DE","type":"education","lineage":["https://openalex.org/I94509681"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Mark Albers","raw_affiliation_strings":["Institute of Computer and Network Engineering (IDA) TU Braunschweig, Braunschweig, Germany"],"affiliations":[{"raw_affiliation_string":"Institute of Computer and Network Engineering (IDA) TU Braunschweig, Braunschweig, Germany","institution_ids":["https://openalex.org/I94509681"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088421111","display_name":"Johannes Schlatow","orcid":"https://orcid.org/0000-0003-0654-4618"},"institutions":[{"id":"https://openalex.org/I94509681","display_name":"Technische Universit\u00e4t Braunschweig","ror":"https://ror.org/010nsgg66","country_code":"DE","type":"education","lineage":["https://openalex.org/I94509681"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Johannes Schlatow","raw_affiliation_strings":["Institute of Computer and Network Engineering (IDA) TU Braunschweig, Braunschweig, Germany"],"affiliations":[{"raw_affiliation_string":"Institute of Computer and Network Engineering (IDA) TU Braunschweig, Braunschweig, Germany","institution_ids":["https://openalex.org/I94509681"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058037811","display_name":"Bj\u00f6rn Fiethe","orcid":"https://orcid.org/0000-0002-7915-6723"},"institutions":[{"id":"https://openalex.org/I94509681","display_name":"Technische Universit\u00e4t Braunschweig","ror":"https://ror.org/010nsgg66","country_code":"DE","type":"education","lineage":["https://openalex.org/I94509681"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Bjorn Fiethe","raw_affiliation_strings":["Institute of Computer and Network Engineering (IDA) TU Braunschweig, Braunschweig, Germany"],"affiliations":[{"raw_affiliation_string":"Institute of Computer and Network Engineering (IDA) TU Braunschweig, Braunschweig, Germany","institution_ids":["https://openalex.org/I94509681"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066794501","display_name":"H. Michalik","orcid":null},"institutions":[{"id":"https://openalex.org/I94509681","display_name":"Technische Universit\u00e4t Braunschweig","ror":"https://ror.org/010nsgg66","country_code":"DE","type":"education","lineage":["https://openalex.org/I94509681"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Harald Michalik","raw_affiliation_strings":["Institute of Computer and Network Engineering (IDA) TU Braunschweig, Braunschweig, Germany"],"affiliations":[{"raw_affiliation_string":"Institute of Computer and Network Engineering (IDA) TU Braunschweig, Braunschweig, Germany","institution_ids":["https://openalex.org/I94509681"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076288432","display_name":"Phillip Keldenich","orcid":"https://orcid.org/0000-0002-6677-5090"},"institutions":[{"id":"https://openalex.org/I94509681","display_name":"Technische Universit\u00e4t Braunschweig","ror":"https://ror.org/010nsgg66","country_code":"DE","type":"education","lineage":["https://openalex.org/I94509681"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Phillip Keldenich","raw_affiliation_strings":["Algorithms Group TU Braunschweig, Braunschweig, Germany"],"affiliations":[{"raw_affiliation_string":"Algorithms Group TU Braunschweig, Braunschweig, Germany","institution_ids":["https://openalex.org/I94509681"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5015542807","display_name":"S\u00e1ndor P. Fekete","orcid":"https://orcid.org/0000-0002-9062-4241"},"institutions":[{"id":"https://openalex.org/I94509681","display_name":"Technische Universit\u00e4t Braunschweig","ror":"https://ror.org/010nsgg66","country_code":"DE","type":"education","lineage":["https://openalex.org/I94509681"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"S'andor P. Fekete","raw_affiliation_strings":["Algorithms Group TU Braunschweig, Braunschweig, Germany"],"affiliations":[{"raw_affiliation_string":"Algorithms Group TU Braunschweig, Braunschweig, Germany","institution_ids":["https://openalex.org/I94509681"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5083715561"],"corresponding_institution_ids":["https://openalex.org/I94509681"],"apc_list":null,"apc_paid":null,"fwci":1.5764,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.83833372,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"66","last_page":"73"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8422499895095825},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7155498266220093},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.6988736391067505},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6426346302032471},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.6120411157608032},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5702109932899475},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5498533248901367},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.523938000202179},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.4599899351596832},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.45860299468040466},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4414740800857544},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4355927109718323},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41225147247314453},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1755104959011078},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.08756890892982483}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8422499895095825},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7155498266220093},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.6988736391067505},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6426346302032471},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.6120411157608032},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5702109932899475},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5498533248901367},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.523938000202179},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.4599899351596832},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.45860299468040466},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4414740800857544},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4355927109718323},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41225147247314453},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1755104959011078},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.08756890892982483},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ahs.2018.8541481","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ahs.2018.8541481","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.800000011920929}],"awards":[{"id":"https://openalex.org/G3330351792","display_name":null,"funder_award_id":"FOR 1800","funder_id":"https://openalex.org/F4320320879","funder_display_name":"Deutsche Forschungsgemeinschaft"}],"funders":[{"id":"https://openalex.org/F4320320879","display_name":"Deutsche Forschungsgemeinschaft","ror":"https://ror.org/018mejw64"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1986744267","https://openalex.org/W2141418654","https://openalex.org/W2164423474","https://openalex.org/W2202604684","https://openalex.org/W2280749311","https://openalex.org/W2381016038","https://openalex.org/W2505901125","https://openalex.org/W2514703751","https://openalex.org/W2580284127","https://openalex.org/W2790522917","https://openalex.org/W6726300596","https://openalex.org/W6749036726"],"related_works":["https://openalex.org/W2810427553","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W4249632163","https://openalex.org/W1760305469","https://openalex.org/W2797161794","https://openalex.org/W2073075351","https://openalex.org/W2340647897","https://openalex.org/W2808484818","https://openalex.org/W1574948540"],"abstract_inverted_index":{"ARM-FPGA":[0],"coupled":[1],"platforms":[2],"allow":[3],"accelerating":[4],"the":[5,14,43,102],"computation":[6,18],"of":[7,20,85],"specific":[8],"algorithms":[9],"by":[10,32],"executing":[11],"them":[12],"in":[13,42,92],"FPGA":[15],"fabric.":[16],"Several":[17],"steps":[19],"our":[21],"case":[22],"study":[23],"for":[24,101],"a":[25,63],"stereo":[26],"vision":[27],"application":[28],"have":[29],"been":[30],"accelerated":[31],"hardware":[33,40,86],"implementations.":[34],"Dynamic":[35],"Partial":[36],"Reconfiguration":[37],"places":[38],"these":[39],"tasks":[41],"programmable":[44],"logic":[45],"at":[46],"appropriate":[47],"times.":[48],"For":[49],"an":[50],"efficient":[51],"scheduling,":[52],"it":[53],"needs":[54],"to":[55,61],"be":[56],"decided":[57],"when":[58],"and":[59,72,83,99,105],"where":[60],"execute":[62],"task.":[64],"Although":[65],"there":[66],"already":[67],"exist":[68],"hardware/software":[69],"scheduling":[70,89],"strategies":[71],"algorithms,":[73],"none":[74],"exploit":[75],"all":[76],"possible":[77],"optimization":[78],"techniques:":[79],"re-use,":[80],"prefetching,":[81],"parallelization,":[82],"pipelining":[84],"tasks.":[87],"The":[88],"algorithm":[90],"proposed":[91],"this":[93,96],"paper":[94],"takes":[95],"into":[97],"account":[98],"optimizes":[100],"objectives":[103],"latency/throughput":[104],"power/energy.":[106]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":4},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":3}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-10-10T00:00:00"}