{"id":"https://openalex.org/W2518448677","doi":"https://doi.org/10.1109/actea.2016.7560104","title":"FPGA realization of ALU for mobile GPU","display_name":"FPGA realization of ALU for mobile GPU","publication_year":2016,"publication_date":"2016-07-01","ids":{"openalex":"https://openalex.org/W2518448677","doi":"https://doi.org/10.1109/actea.2016.7560104","mag":"2518448677"},"language":"en","primary_location":{"id":"doi:10.1109/actea.2016.7560104","is_oa":false,"landing_page_url":"https://doi.org/10.1109/actea.2016.7560104","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 3rd International Conference on Advances in Computational Tools for Engineering Applications (ACTEA)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5091151249","display_name":"Mohammed F. Tolba","orcid":"https://orcid.org/0000-0002-6412-290X"},"institutions":[{"id":"https://openalex.org/I57629906","display_name":"Nile University","ror":"https://ror.org/03cg7cp61","country_code":"EG","type":"education","lineage":["https://openalex.org/I57629906"]}],"countries":["EG"],"is_corresponding":true,"raw_author_name":"Mohammed F. Tolba","raw_affiliation_strings":["Nanoelectronics Integrated Systems Center (NISC), Nile University, Giza, Egypt"],"affiliations":[{"raw_affiliation_string":"Nanoelectronics Integrated Systems Center (NISC), Nile University, Giza, Egypt","institution_ids":["https://openalex.org/I57629906"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035566088","display_name":"Ahmed H. Madian","orcid":"https://orcid.org/0000-0001-8313-8088"},"institutions":[{"id":"https://openalex.org/I4210148873","display_name":"National Center of Radiobiology and Radiation Protection","ror":"https://ror.org/058kdrc56","country_code":"BG","type":"healthcare","lineage":["https://openalex.org/I4210148873"]},{"id":"https://openalex.org/I57629906","display_name":"Nile University","ror":"https://ror.org/03cg7cp61","country_code":"EG","type":"education","lineage":["https://openalex.org/I57629906"]}],"countries":["BG","EG"],"is_corresponding":false,"raw_author_name":"Ahmed H. Madian","raw_affiliation_strings":["Nanoelectronics Integrated Systems Center (NISC), Nile University, Giza, Egypt","Radiation Engineering Dept, NCRRT"],"affiliations":[{"raw_affiliation_string":"Nanoelectronics Integrated Systems Center (NISC), Nile University, Giza, Egypt","institution_ids":["https://openalex.org/I57629906"]},{"raw_affiliation_string":"Radiation Engineering Dept, NCRRT","institution_ids":["https://openalex.org/I4210148873"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069997789","display_name":"Ahmed G. Radwan","orcid":"https://orcid.org/0000-0002-6119-8482"},"institutions":[{"id":"https://openalex.org/I145487455","display_name":"Cairo University","ror":"https://ror.org/03q21mh05","country_code":"EG","type":"education","lineage":["https://openalex.org/I145487455"]},{"id":"https://openalex.org/I57629906","display_name":"Nile University","ror":"https://ror.org/03cg7cp61","country_code":"EG","type":"education","lineage":["https://openalex.org/I57629906"]}],"countries":["EG"],"is_corresponding":false,"raw_author_name":"Ahmed G. Radwan","raw_affiliation_strings":["Engineering Mathematics and Physics Department, Cairo University, Egypt","Nanoelectronics Integrated Systems Center (NISC), Nile University, Giza, Egypt"],"affiliations":[{"raw_affiliation_string":"Engineering Mathematics and Physics Department, Cairo University, Egypt","institution_ids":["https://openalex.org/I145487455"]},{"raw_affiliation_string":"Nanoelectronics Integrated Systems Center (NISC), Nile University, Giza, Egypt","institution_ids":["https://openalex.org/I57629906"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5091151249"],"corresponding_institution_ids":["https://openalex.org/I57629906"],"apc_list":null,"apc_paid":null,"fwci":1.2613,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.78991913,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"16","last_page":"20"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7898361682891846},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7359079122543335},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7155520915985107},{"id":"https://openalex.org/keywords/arithmetic-logic-unit","display_name":"Arithmetic logic unit","score":0.6648068428039551},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6229439973831177},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6178963780403137},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5647193193435669},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.49989819526672363},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.4690934419631958},{"id":"https://openalex.org/keywords/shader","display_name":"Shader","score":0.45974379777908325},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4322965145111084},{"id":"https://openalex.org/keywords/double-precision-floating-point-format","display_name":"Double-precision floating-point format","score":0.43032991886138916},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.4170699715614319},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.40378931164741516},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2212631106376648},{"id":"https://openalex.org/keywords/graphics","display_name":"Graphics","score":0.19266721606254578},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11706233024597168},{"id":"https://openalex.org/keywords/computer-graphics","display_name":"Computer graphics (images)","score":0.10293200612068176}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7898361682891846},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7359079122543335},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7155520915985107},{"id":"https://openalex.org/C100276221","wikidata":"https://www.wikidata.org/wiki/Q192903","display_name":"Arithmetic logic unit","level":2,"score":0.6648068428039551},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6229439973831177},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6178963780403137},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5647193193435669},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.49989819526672363},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4690934419631958},{"id":"https://openalex.org/C177681979","wikidata":"https://www.wikidata.org/wiki/Q633182","display_name":"Shader","level":3,"score":0.45974379777908325},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4322965145111084},{"id":"https://openalex.org/C35912277","wikidata":"https://www.wikidata.org/wiki/Q1243369","display_name":"Double-precision floating-point format","level":3,"score":0.43032991886138916},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.4170699715614319},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.40378931164741516},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2212631106376648},{"id":"https://openalex.org/C21442007","wikidata":"https://www.wikidata.org/wiki/Q1027879","display_name":"Graphics","level":2,"score":0.19266721606254578},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11706233024597168},{"id":"https://openalex.org/C121684516","wikidata":"https://www.wikidata.org/wiki/Q7600677","display_name":"Computer graphics (images)","level":1,"score":0.10293200612068176},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/actea.2016.7560104","is_oa":false,"landing_page_url":"https://doi.org/10.1109/actea.2016.7560104","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 3rd International Conference on Advances in Computational Tools for Engineering Applications (ACTEA)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.6899999976158142,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1584008964","https://openalex.org/W1678606207","https://openalex.org/W2124063495","https://openalex.org/W2134340157","https://openalex.org/W2142853511","https://openalex.org/W2151743818","https://openalex.org/W2163287526","https://openalex.org/W2532306963","https://openalex.org/W2539871550","https://openalex.org/W2543035391","https://openalex.org/W2567646662","https://openalex.org/W4210673018"],"related_works":["https://openalex.org/W2999386785","https://openalex.org/W2596938593","https://openalex.org/W2062256252","https://openalex.org/W2056812584","https://openalex.org/W2325691454","https://openalex.org/W2037154093","https://openalex.org/W4394241945","https://openalex.org/W2614101859","https://openalex.org/W2596474508","https://openalex.org/W1531851644"],"abstract_inverted_index":{"Arithmetic":[0],"Logic":[1],"Unit":[2],"(ALU)":[3],"is":[4,34,68],"the":[5,19,24,27,30,62],"most":[6],"important":[7],"component":[8],"of":[9,29],"processors.":[10],"All":[11],"arithmetic":[12],"and":[13,26,40,50,72],"logical":[14],"computations":[15],"are":[16,55],"performed":[17],"inside":[18],"ALU.":[20,31],"This":[21],"paper":[22],"presents":[23],"design":[25,33],"implementation":[28],"The":[32,45,65],"based":[35],"on":[36],"Approximated":[37],"Precision":[38],"Shader":[39],"Look-Up":[41],"Table":[42],"(LUT)":[43],"multiplier.":[44],"lookup":[46],"table,":[47],"Wallace":[48],"tree,":[49],"Carry":[51],"Look-ahead":[52],"Adder":[53],"(CLA)":[54],"used":[56],"in":[57],"combination":[58],"to":[59],"speed":[60],"up":[61],"multiplier":[63],"operation.":[64],"proposed":[66],"ALU":[67],"designed":[69],"using":[70,74],"Verilog":[71],"verified":[73],"Xilinx":[75],"Virtex-5":[76],"XC5VLX30":[77],"FPGA.":[78]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}