{"id":"https://openalex.org/W2547788737","doi":"https://doi.org/10.1109/acssc.2011.6190048","title":"Fine-grain Reconfigurable Functional Unit for embedded processors","display_name":"Fine-grain Reconfigurable Functional Unit for embedded processors","publication_year":2011,"publication_date":"2011-11-01","ids":{"openalex":"https://openalex.org/W2547788737","doi":"https://doi.org/10.1109/acssc.2011.6190048","mag":"2547788737"},"language":"en","primary_location":{"id":"doi:10.1109/acssc.2011.6190048","is_oa":false,"landing_page_url":"https://doi.org/10.1109/acssc.2011.6190048","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028297120","display_name":"G.C. Cardarilli","orcid":"https://orcid.org/0000-0002-7444-876X"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gian Carlo Cardarilli","raw_affiliation_strings":["Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063300969","display_name":"Luca Di Nunzio","orcid":"https://orcid.org/0000-0002-4312-7939"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]},{"id":"https://openalex.org/I2801039369","display_name":"Marconi University","ror":"https://ror.org/00j0rk173","country_code":"IT","type":"education","lineage":["https://openalex.org/I2801039369"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Di Nunzio","raw_affiliation_strings":["Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy","Universit\u00e0 degli Studi |Guglielmo Marconi|, Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Universit\u00e0 degli Studi |Guglielmo Marconi|, Rome, Italy","institution_ids":["https://openalex.org/I2801039369"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048482308","display_name":"Rocco Fazzolari","orcid":"https://orcid.org/0000-0002-7383-2663"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Rocco Fazzolari","raw_affiliation_strings":["Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000963583","display_name":"M. Re","orcid":"https://orcid.org/0000-0001-9046-1318"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Re","raw_affiliation_strings":["Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Roma Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1902,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.46264316,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"488","last_page":"492"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6418659687042236},{"id":"https://openalex.org/keywords/unit","display_name":"Unit (ring theory)","score":0.5287948250770569},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.41792184114456177},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4116184711456299},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41056033968925476},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40888214111328125},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.26159223914146423},{"id":"https://openalex.org/keywords/psychology","display_name":"Psychology","score":0.06716597080230713}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6418659687042236},{"id":"https://openalex.org/C122637931","wikidata":"https://www.wikidata.org/wiki/Q118084","display_name":"Unit (ring theory)","level":2,"score":0.5287948250770569},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.41792184114456177},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4116184711456299},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41056033968925476},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40888214111328125},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26159223914146423},{"id":"https://openalex.org/C15744967","wikidata":"https://www.wikidata.org/wiki/Q9418","display_name":"Psychology","level":0,"score":0.06716597080230713},{"id":"https://openalex.org/C145420912","wikidata":"https://www.wikidata.org/wiki/Q853077","display_name":"Mathematics education","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/acssc.2011.6190048","is_oa":false,"landing_page_url":"https://doi.org/10.1109/acssc.2011.6190048","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR)","raw_type":"proceedings-article"},{"id":"pmh:oai:art.torvergata.it:2108/104295","is_oa":false,"landing_page_url":"http://hdl.handle.net/2108/104295","pdf_url":null,"source":{"id":"https://openalex.org/S4306400993","display_name":"Cineca Institutional Research Information System (Tor Vergata University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I116067653","host_organization_name":"University of Rome Tor Vergata","host_organization_lineage":["https://openalex.org/I116067653"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4099999964237213,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1967767709","https://openalex.org/W1969693240","https://openalex.org/W2098129944","https://openalex.org/W2128812806","https://openalex.org/W2132918567","https://openalex.org/W2148911285","https://openalex.org/W2149307572","https://openalex.org/W2159126185","https://openalex.org/W2169167556","https://openalex.org/W2396231625","https://openalex.org/W4252466729"],"related_works":["https://openalex.org/W611386996","https://openalex.org/W2371343292","https://openalex.org/W629290331","https://openalex.org/W617685022","https://openalex.org/W1509983653","https://openalex.org/W3215563689","https://openalex.org/W610590827","https://openalex.org/W591599671","https://openalex.org/W1556748146","https://openalex.org/W1990796017"],"abstract_inverted_index":{"In":[0,13,60,104],"standard":[1],"word-oriented":[2],"microprocessors,":[3],"the":[4,10,29,63,101,109,113],"processing":[5],"of":[6,42,112,121],"short":[7],"data":[8],"decreases":[9],"computation":[11],"performance.":[12],"order":[14],"to":[15,85],"overcome":[16],"this":[17,105],"issue":[18],"various":[19],"methods":[20],"based":[21,55,72],"on":[22,56,73],"reconfigurable":[23,44,51],"architectures":[24],"have":[25],"been":[26],"presented":[27],"in":[28,127],"literature":[30],"[1]":[31],"[2]":[32],"[3].":[33],"These":[34],"structures":[35],"are":[36],"normally":[37],"composed":[38],"by":[39],"an":[40,128],"array":[41],"elementary":[43,50],"cells.":[45],"A":[46],"common":[47],"solution":[48],"for":[49],"cells":[52],"realization":[53],"is":[54,84],"Look-Up":[57],"Tables":[58],"(LUTs).":[59],"[4]":[61],"[5]":[62],"authors":[64],"proposed":[65,114],"a":[66,87],"new":[67,88],"Reconfigurable":[68],"Functional":[69],"Unit":[70],"(RFU)":[71],"full":[74],"adders":[75],"and":[76,95,123],"reprogrammable":[77],"interconnects":[78],"named":[79],"ADAPTO.":[80],"The":[81],"final":[82],"aim":[83],"obtain":[86],"structure":[89,115],"that":[90],"requires":[91],"less":[92],"silicon":[93],"area":[94],"power,":[96],"being":[97],"ever":[98],"faster":[99],"than":[100],"\u201ctraditional\u201d":[102],"solutions.":[103],"paper":[106],"we":[107],"present":[108],"main":[110],"characteristics":[111],"evaluating":[116],"its":[117],"performance":[118],"(in":[119],"terms":[120],"speed-up":[122],"complexity)":[124],"when":[125],"integrated":[126],"embedded":[129],"processor.":[130]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":7},{"year":2017,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-08-12T21:12:35.861297","created_date":"2025-10-10T00:00:00"}
