{"id":"https://openalex.org/W3204573923","doi":"https://doi.org/10.1109/acit52158.2021.9548117","title":"A Survey of Machine Learning Methods and Applications in Electronic Design Automation","display_name":"A Survey of Machine Learning Methods and Applications in Electronic Design Automation","publication_year":2021,"publication_date":"2021-09-15","ids":{"openalex":"https://openalex.org/W3204573923","doi":"https://doi.org/10.1109/acit52158.2021.9548117","mag":"3204573923"},"language":"en","primary_location":{"id":"doi:10.1109/acit52158.2021.9548117","is_oa":false,"landing_page_url":"https://doi.org/10.1109/acit52158.2021.9548117","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 11th International Conference on Advanced Computer Information Technologies (ACIT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037264394","display_name":"Vladyslav Hamolia","orcid":"https://orcid.org/0000-0003-2444-0775"},"institutions":[{"id":"https://openalex.org/I98435010","display_name":"Lviv Polytechnic National University","ror":"https://ror.org/0542q3127","country_code":"UA","type":"education","lineage":["https://openalex.org/I98435010"]}],"countries":["UA"],"is_corresponding":true,"raw_author_name":"Vladyslav Hamolia","raw_affiliation_strings":["Lviv Polytechnic National University,Department of Information Technologies Security,Lviv,Ukraine","Department of Information Technologies Security, Lviv Polytechnic National University, Lviv, Ukraine"],"affiliations":[{"raw_affiliation_string":"Lviv Polytechnic National University,Department of Information Technologies Security,Lviv,Ukraine","institution_ids":["https://openalex.org/I98435010"]},{"raw_affiliation_string":"Department of Information Technologies Security, Lviv Polytechnic National University, Lviv, Ukraine","institution_ids":["https://openalex.org/I98435010"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020022335","display_name":"Viktor Melnyk","orcid":"https://orcid.org/0000-0002-5046-8002"},"institutions":[{"id":"https://openalex.org/I4210137370","display_name":"Institute of Mathematics","ror":"https://ror.org/04hrrh248","country_code":"PL","type":"facility","lineage":["https://openalex.org/I4210137370","https://openalex.org/I99542240"]},{"id":"https://openalex.org/I111702420","display_name":"John Paul II Catholic University of Lublin","ror":"https://ror.org/04qyefj88","country_code":"PL","type":"education","lineage":["https://openalex.org/I111702420"]},{"id":"https://openalex.org/I98435010","display_name":"Lviv Polytechnic National University","ror":"https://ror.org/0542q3127","country_code":"UA","type":"education","lineage":["https://openalex.org/I98435010"]}],"countries":["PL","UA"],"is_corresponding":false,"raw_author_name":"Viktor Melnyk","raw_affiliation_strings":["Lviv Polytechnic National University,Department of Information Technologies Security,Lviv,Ukraine","Department of Information Technologies Security, Lviv Polytechnic National University, Lviv, Ukraine","Institute of Mathematics, Informatics and Landscape Architecture, John Paul II Catholic University of Lublin, Lublin, Poland"],"affiliations":[{"raw_affiliation_string":"Lviv Polytechnic National University,Department of Information Technologies Security,Lviv,Ukraine","institution_ids":["https://openalex.org/I98435010"]},{"raw_affiliation_string":"Department of Information Technologies Security, Lviv Polytechnic National University, Lviv, Ukraine","institution_ids":["https://openalex.org/I98435010"]},{"raw_affiliation_string":"Institute of Mathematics, Informatics and Landscape Architecture, John Paul II Catholic University of Lublin, Lublin, Poland","institution_ids":["https://openalex.org/I111702420","https://openalex.org/I4210137370"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5037264394"],"corresponding_institution_ids":["https://openalex.org/I98435010"],"apc_list":null,"apc_paid":null,"fwci":1.103,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.77379265,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"757","last_page":"760"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.8416087627410889},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.7796141505241394},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.726369321346283},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.696412980556488},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6905505061149597},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.6444759964942932},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5593889951705933},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5548560619354248},{"id":"https://openalex.org/keywords/field","display_name":"Field (mathematics)","score":0.49612388014793396},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.48276057839393616},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.47759342193603516},{"id":"https://openalex.org/keywords/electronics","display_name":"Electronics","score":0.47615882754325867},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.47145089507102966},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4412800669670105},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4386083781719208},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.43659716844558716},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.4247104525566101},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.377651184797287},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.273497998714447},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1914096176624298},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11455860733985901},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08455494046211243}],"concepts":[{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.8416087627410889},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.7796141505241394},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.726369321346283},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.696412980556488},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6905505061149597},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.6444759964942932},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5593889951705933},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5548560619354248},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.49612388014793396},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.48276057839393616},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.47759342193603516},{"id":"https://openalex.org/C138331895","wikidata":"https://www.wikidata.org/wiki/Q11650","display_name":"Electronics","level":2,"score":0.47615882754325867},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.47145089507102966},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4412800669670105},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4386083781719208},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.43659716844558716},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.4247104525566101},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.377651184797287},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.273497998714447},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1914096176624298},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11455860733985901},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08455494046211243},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/acit52158.2021.9548117","is_oa":false,"landing_page_url":"https://doi.org/10.1109/acit52158.2021.9548117","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 11th International Conference on Advanced Computer Information Technologies (ACIT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6600000262260437,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W162536958","https://openalex.org/W1511071348","https://openalex.org/W1675335411","https://openalex.org/W1999116995","https://openalex.org/W2002525234","https://openalex.org/W2018351041","https://openalex.org/W2074520226","https://openalex.org/W2099184857","https://openalex.org/W2121359873","https://openalex.org/W2124923188","https://openalex.org/W2131294285","https://openalex.org/W2133882425","https://openalex.org/W2161629461","https://openalex.org/W2328615082","https://openalex.org/W2381518922","https://openalex.org/W2889669826","https://openalex.org/W2897505503","https://openalex.org/W2903881552","https://openalex.org/W2939908742","https://openalex.org/W2998169401","https://openalex.org/W3012124806","https://openalex.org/W3036947539","https://openalex.org/W3116075305","https://openalex.org/W3134987482","https://openalex.org/W3140720939","https://openalex.org/W3151205559","https://openalex.org/W6630531834","https://openalex.org/W6679750918","https://openalex.org/W6788039050"],"related_works":["https://openalex.org/W4253195573","https://openalex.org/W2020934033","https://openalex.org/W2051886008","https://openalex.org/W3042858012","https://openalex.org/W2743305891","https://openalex.org/W1716153929","https://openalex.org/W3011978806","https://openalex.org/W3205162826","https://openalex.org/W1975701649","https://openalex.org/W2610167993"],"abstract_inverted_index":{"Over":[0],"the":[1,4,16,21,38,48,73,81,88,112,115,147,156],"past":[2,89],"decades,":[3],"domain":[5],"of":[6,15,47,91],"electronic":[7,39],"circuits":[8,27],"design":[9,40,64,117,123],"continues":[10],"transitioning":[11],"to":[12,19,61,140],"wider":[13],"usage":[14],"automation":[17,41],"tools":[18],"overcome":[20],"human":[22],"level":[23],"limitations,":[24],"where":[25],"integrated":[26],"(IC)":[28],"were":[29],"designed":[30],"by":[31],"hand":[32],"and":[33,53,85,107,128],"manually":[34],"arranged.":[35],"Experts":[36],"in":[37,80,114,138,151],"(EDA)":[42],"industry":[43],"agree":[44],"that":[45,76,109],"most":[46],"Application-Specific":[49],"Integrated":[50],"Circuit":[51],"(ASIC)":[52],"Field-Programmable":[54],"Gate":[55],"Arrays":[56],"(FPGA)":[57],"designers":[58],"will":[59],"turn":[60],"high-level":[62],"automated":[63],"methodologies":[65],"soon.":[66],"The":[67,130],"main":[68],"reason":[69],"for":[70,97],"this":[71],"is":[72],"technology":[74],"improvements":[75,137],"have":[77,134],"taken":[78],"place":[79],"EDA":[82,98],"tools,":[83],"hardware,":[84],"software.":[86],"In":[87],"couple":[90],"years,":[92],"Machine":[93],"Learning":[94],"(ML)":[95],"achievements":[96],"turned":[99],"into":[100],"a":[101],"separate":[102],"field":[103],"with":[104],"new":[105],"studies":[106],"methods":[108],"enclose":[110],"all":[111],"phases":[113],"chip":[116],"flow,":[118],"such":[119],"as":[120],"logic":[121],"synthesis,":[122],"space":[124],"reduction,":[125],"exploration,":[126],"placement,":[127],"routing.":[129],"latest":[131],"ML-build":[132],"approaches":[133],"shown":[135],"considerable":[136],"contrast":[139],"established":[141],"traditional":[142],"methods.":[143],"This":[144],"paper":[145],"covers":[146],"newest":[148],"ML":[149],"algorithms":[150],"FPGA":[152],"device":[153],"design,":[154],"emphasizing":[155],"recent":[157],"research":[158],"benchmarks\u2019":[159],"realizations.":[160]},"counts_by_year":[{"year":2025,"cited_by_count":6},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
