{"id":"https://openalex.org/W7131437053","doi":"https://doi.org/10.1109/access.2026.3667909","title":"Computational Bayesian Experimental Design and Inference for Assisted Linear Circuit Prototype Debug","display_name":"Computational Bayesian Experimental Design and Inference for Assisted Linear Circuit Prototype Debug","publication_year":2026,"publication_date":"2026-01-01","ids":{"openalex":"https://openalex.org/W7131437053","doi":"https://doi.org/10.1109/access.2026.3667909"},"language":null,"primary_location":{"id":"doi:10.1109/access.2026.3667909","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2026.3667909","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1109/access.2026.3667909","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011773556","display_name":"Ian E. J. Hill","orcid":"https://orcid.org/0000-0001-9782-8522"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Ian Hill","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of British Columbia, Vancouver, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109993328","display_name":"Frank Wood","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Frank Wood","raw_affiliation_strings":["Department of Computer Science, The University of British Columbia, Vancouver, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, The University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5126829832","display_name":"Andr\u00e9 Ivanov","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Andr\u00e9 Ivanov","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of British Columbia, Vancouver, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5011773556"],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":{"value":1850,"currency":"USD","value_usd":1850},"apc_paid":{"value":1850,"currency":"USD","value_usd":1850},"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.82962428,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"14","issue":null,"first_page":"31241","last_page":"31253"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11798","display_name":"Optimal Experimental Design Methods","score":0.41339999437332153,"subfield":{"id":"https://openalex.org/subfields/1803","display_name":"Management Science and Operations Research"},"field":{"id":"https://openalex.org/fields/18","display_name":"Decision Sciences"},"domain":{"id":"https://openalex.org/domains/2","display_name":"Social Sciences"}},"topics":[{"id":"https://openalex.org/T11798","display_name":"Optimal Experimental Design Methods","score":0.41339999437332153,"subfield":{"id":"https://openalex.org/subfields/1803","display_name":"Management Science and Operations Research"},"field":{"id":"https://openalex.org/fields/18","display_name":"Decision Sciences"},"domain":{"id":"https://openalex.org/domains/2","display_name":"Social Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.08910000324249268,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10928","display_name":"Probabilistic and Robust Engineering Design","score":0.0723000019788742,"subfield":{"id":"https://openalex.org/subfields/1804","display_name":"Statistics, Probability and Uncertainty"},"field":{"id":"https://openalex.org/fields/18","display_name":"Decision Sciences"},"domain":{"id":"https://openalex.org/domains/2","display_name":"Social Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.8950999975204468},{"id":"https://openalex.org/keywords/probabilistic-logic","display_name":"Probabilistic logic","score":0.5537999868392944},{"id":"https://openalex.org/keywords/inference","display_name":"Inference","score":0.5347999930381775},{"id":"https://openalex.org/keywords/bayesian-network","display_name":"Bayesian network","score":0.41839998960494995},{"id":"https://openalex.org/keywords/bayesian-probability","display_name":"Bayesian probability","score":0.3817000091075897},{"id":"https://openalex.org/keywords/statistical-inference","display_name":"Statistical inference","score":0.36970001459121704},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.3646000027656555}],"concepts":[{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.8950999975204468},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.789900004863739},{"id":"https://openalex.org/C49937458","wikidata":"https://www.wikidata.org/wiki/Q2599292","display_name":"Probabilistic logic","level":2,"score":0.5537999868392944},{"id":"https://openalex.org/C2776214188","wikidata":"https://www.wikidata.org/wiki/Q408386","display_name":"Inference","level":2,"score":0.5347999930381775},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.428600013256073},{"id":"https://openalex.org/C33724603","wikidata":"https://www.wikidata.org/wiki/Q812540","display_name":"Bayesian network","level":2,"score":0.41839998960494995},{"id":"https://openalex.org/C107673813","wikidata":"https://www.wikidata.org/wiki/Q812534","display_name":"Bayesian probability","level":2,"score":0.3817000091075897},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3801000118255615},{"id":"https://openalex.org/C134261354","wikidata":"https://www.wikidata.org/wiki/Q938438","display_name":"Statistical inference","level":2,"score":0.36970001459121704},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3646000027656555},{"id":"https://openalex.org/C160234255","wikidata":"https://www.wikidata.org/wiki/Q812535","display_name":"Bayesian inference","level":3,"score":0.3499000072479248},{"id":"https://openalex.org/C1009929","wikidata":"https://www.wikidata.org/wiki/Q179550","display_name":"Software bug","level":3,"score":0.34610000252723694},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3418999910354614},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3407000005245209},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.3197000026702881},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.29989999532699585},{"id":"https://openalex.org/C87007009","wikidata":"https://www.wikidata.org/wiki/Q210832","display_name":"Statistical hypothesis testing","level":2,"score":0.2980000078678131},{"id":"https://openalex.org/C114289077","wikidata":"https://www.wikidata.org/wiki/Q3284399","display_name":"Statistical model","level":2,"score":0.29670000076293945},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.2962999939918518},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.29589998722076416},{"id":"https://openalex.org/C163175372","wikidata":"https://www.wikidata.org/wiki/Q3339222","display_name":"Linear model","level":2,"score":0.2906000018119812},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26339998841285706}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/access.2026.3667909","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2026.3667909","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1109/access.2026.3667909","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2026.3667909","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Circuit":[0],"prototype":[1],"debug":[2,26,44,80,98],"can":[3],"be":[4],"challenging":[5],"for":[6,11,81],"students":[7],"and":[8,35,63,74],"novice":[9],"engineers":[10],"which":[12],"emerging":[13],"intelligent":[14],"Bayesian":[15,32],"statistical":[16],"methods":[17],"have":[18],"potential":[19],"application.":[20],"We":[21],"introduce":[22],"an":[23],"automated":[24],"assisted":[25,79],"methodology":[27],"using":[28],"advancements":[29],"in":[30,94],"computational":[31],"experimental":[33],"design":[34,59],"inference":[36],"to":[37],"automate":[38],"all":[39],"cognitive":[40],"sub-problems":[41],"of":[42,60,65,87],"the":[43],"process.":[45],"A":[46],"broad":[47],"probabilistic":[48],"defect":[49,66],"model":[50],"is":[51],"injected":[52],"into":[53],"a":[54],"target":[55,88],"circuit":[56,97,107],"topology,":[57],"enabling":[58],"maximally-informative":[61],"tests":[62],"assessment":[64],"probabilities":[67],"following":[68],"test":[69],"observations.":[70],"The":[71],"topology-agnostic":[72],"approach":[73],"efficient":[75],"implementation":[76],"enables":[77],"real-time":[78],"laboratory":[82],"contexts":[83],"without":[84],"prior":[85],"analysis":[86],"circuits.":[89],"Case":[90],"studies":[91],"demonstrate":[92],"effectiveness":[93],"tackling":[95],"linear":[96],"with":[99],"improved":[100],"capabilities":[101],"over":[102],"literature":[103],"on":[104],"integrated":[105],"analog":[106],"debug.":[108]},"counts_by_year":[],"updated_date":"2026-03-04T07:04:00.330322","created_date":"2026-02-26T00:00:00"}