{"id":"https://openalex.org/W7126211951","doi":"https://doi.org/10.1109/access.2026.3659527","title":"Analog Integrated Circuit Optimization With an Enhanced Adaptive Quantum Genetic Algorithm","display_name":"Analog Integrated Circuit Optimization With an Enhanced Adaptive Quantum Genetic Algorithm","publication_year":2026,"publication_date":"2026-01-01","ids":{"openalex":"https://openalex.org/W7126211951","doi":"https://doi.org/10.1109/access.2026.3659527"},"language":null,"primary_location":{"id":"doi:10.1109/access.2026.3659527","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2026.3659527","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1109/access.2026.3659527","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5124402506","display_name":"P Sridhar","orcid":null},"institutions":[{"id":"https://openalex.org/I876193797","display_name":"Vellore Institute of Technology University","ror":"https://ror.org/00qzypv28","country_code":"IN","type":"education","lineage":["https://openalex.org/I876193797"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"P. Sridhar","raw_affiliation_strings":["School of Electronics Engineering, Vellore Institute of Technology, Vellore, India"],"raw_orcid":"https://orcid.org/0009-0002-8202-8359","affiliations":[{"raw_affiliation_string":"School of Electronics Engineering, Vellore Institute of Technology, Vellore, India","institution_ids":["https://openalex.org/I876193797"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103186457","display_name":"Harish M. Kittur","orcid":null},"institutions":[{"id":"https://openalex.org/I876193797","display_name":"Vellore Institute of Technology University","ror":"https://ror.org/00qzypv28","country_code":"IN","type":"education","lineage":["https://openalex.org/I876193797"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Harish Mallikarjun Kittur","raw_affiliation_strings":["School of Electronics Engineering, Vellore Institute of Technology, Vellore, India"],"raw_orcid":"https://orcid.org/0000-0002-6752-340X","affiliations":[{"raw_affiliation_string":"School of Electronics Engineering, Vellore Institute of Technology, Vellore, India","institution_ids":["https://openalex.org/I876193797"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5124402506"],"corresponding_institution_ids":["https://openalex.org/I876193797"],"apc_list":{"value":1850,"currency":"USD","value_usd":1850},"apc_paid":{"value":1850,"currency":"USD","value_usd":1850},"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.19576576,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"14","issue":null,"first_page":"19205","last_page":"19223"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.3425000011920929,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.3425000011920929,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.2619999945163727,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.18170000612735748,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.614300012588501},{"id":"https://openalex.org/keywords/quantum-computer","display_name":"Quantum computer","score":0.5871999859809875},{"id":"https://openalex.org/keywords/convergence","display_name":"Convergence (economics)","score":0.5557000041007996},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.5503000020980835},{"id":"https://openalex.org/keywords/genetic-algorithm","display_name":"Genetic algorithm","score":0.5218999981880188},{"id":"https://openalex.org/keywords/quantum","display_name":"Quantum","score":0.46860000491142273},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.45980000495910645},{"id":"https://openalex.org/keywords/quantum-gate","display_name":"Quantum gate","score":0.4185999929904938},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4108000099658966},{"id":"https://openalex.org/keywords/quantum-circuit","display_name":"Quantum circuit","score":0.40529999136924744}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7084000110626221},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.614300012588501},{"id":"https://openalex.org/C58053490","wikidata":"https://www.wikidata.org/wiki/Q176555","display_name":"Quantum computer","level":3,"score":0.5871999859809875},{"id":"https://openalex.org/C2777303404","wikidata":"https://www.wikidata.org/wiki/Q759757","display_name":"Convergence (economics)","level":2,"score":0.5557000041007996},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.5503000020980835},{"id":"https://openalex.org/C8880873","wikidata":"https://www.wikidata.org/wiki/Q187787","display_name":"Genetic algorithm","level":2,"score":0.5218999981880188},{"id":"https://openalex.org/C84114770","wikidata":"https://www.wikidata.org/wiki/Q46344","display_name":"Quantum","level":2,"score":0.46860000491142273},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.45980000495910645},{"id":"https://openalex.org/C58849907","wikidata":"https://www.wikidata.org/wiki/Q2118982","display_name":"Quantum gate","level":4,"score":0.4185999929904938},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4108000099658966},{"id":"https://openalex.org/C124148022","wikidata":"https://www.wikidata.org/wiki/Q2122210","display_name":"Quantum circuit","level":5,"score":0.40529999136924744},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.39579999446868896},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.38580000400543213},{"id":"https://openalex.org/C105902424","wikidata":"https://www.wikidata.org/wiki/Q1197129","display_name":"Evolutionary computation","level":2,"score":0.3849000036716461},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.37040001153945923},{"id":"https://openalex.org/C58758708","wikidata":"https://www.wikidata.org/wiki/Q7240233","display_name":"Premature convergence","level":3,"score":0.36320000886917114},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.36169999837875366},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3547999858856201},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3488999903202057},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.3361999988555908},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.33079999685287476},{"id":"https://openalex.org/C74750220","wikidata":"https://www.wikidata.org/wiki/Q2662197","display_name":"Differential evolution","level":2,"score":0.31690001487731934},{"id":"https://openalex.org/C137836250","wikidata":"https://www.wikidata.org/wiki/Q984063","display_name":"Optimization problem","level":2,"score":0.30169999599456787},{"id":"https://openalex.org/C164752517","wikidata":"https://www.wikidata.org/wiki/Q5570875","display_name":"Global optimization","level":2,"score":0.3009999990463257},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.2953999936580658},{"id":"https://openalex.org/C70388272","wikidata":"https://www.wikidata.org/wiki/Q5968558","display_name":"IBM","level":2,"score":0.28690001368522644},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.2831000089645386},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.2768999934196472},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.2757999897003174},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.26820001006126404},{"id":"https://openalex.org/C159149176","wikidata":"https://www.wikidata.org/wiki/Q14489129","display_name":"Evolutionary algorithm","level":2,"score":0.2671000063419342},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2646999955177307},{"id":"https://openalex.org/C137019171","wikidata":"https://www.wikidata.org/wiki/Q2623817","display_name":"Quantum algorithm","level":3,"score":0.262800008058548},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.25999999046325684},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.25760000944137573},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.2535000145435333}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/access.2026.3659527","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2026.3659527","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1109/access.2026.3659527","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2026.3659527","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":50,"referenced_works":["https://openalex.org/W1491101179","https://openalex.org/W1962752774","https://openalex.org/W1964239621","https://openalex.org/W1999357165","https://openalex.org/W2003175917","https://openalex.org/W2003312239","https://openalex.org/W2067964949","https://openalex.org/W2106476087","https://openalex.org/W2115053914","https://openalex.org/W2122274805","https://openalex.org/W2129622254","https://openalex.org/W2168115688","https://openalex.org/W2179731956","https://openalex.org/W2800869073","https://openalex.org/W2968630154","https://openalex.org/W2981377505","https://openalex.org/W2990961515","https://openalex.org/W2997526224","https://openalex.org/W3043883479","https://openalex.org/W3133586392","https://openalex.org/W3213635425","https://openalex.org/W4200230212","https://openalex.org/W4220960087","https://openalex.org/W4223922902","https://openalex.org/W4312525198","https://openalex.org/W4319915084","https://openalex.org/W4321607220","https://openalex.org/W4384818520","https://openalex.org/W4386570149","https://openalex.org/W4387530110","https://openalex.org/W4388240305","https://openalex.org/W4388729366","https://openalex.org/W4389162407","https://openalex.org/W4389776171","https://openalex.org/W4389956218","https://openalex.org/W4391653433","https://openalex.org/W4393972919","https://openalex.org/W4394585761","https://openalex.org/W4400033404","https://openalex.org/W4401070184","https://openalex.org/W4401406949","https://openalex.org/W4401691638","https://openalex.org/W4402592510","https://openalex.org/W4403534914","https://openalex.org/W4403717712","https://openalex.org/W4405619923","https://openalex.org/W4406522596","https://openalex.org/W4408151489","https://openalex.org/W4409282428","https://openalex.org/W4414197065"],"related_works":[],"abstract_inverted_index":{"The":[0,93],"optimization":[1],"of":[2,124,155],"analog":[3,29,100,208],"integrated":[4],"circuit":[5],"synthesis":[6],"is":[7,95,127],"inherently":[8],"a":[9,79,107,110,114,203],"multi-objective":[10],"problem,":[11],"requiring":[12],"the":[13,76,130,149,161,187],"global":[14,86],"optimum":[15],"to":[16,90,147],"satisfy":[17],"all":[18],"critical":[19],"performance":[20],"constraints.":[21],"Classical":[22],"genetic":[23],"algorithms,":[24],"although":[25],"widely":[26],"applied":[27],"in":[28,39,122,172],"design,":[30],"often":[31],"suffer":[32],"from":[33],"slow":[34],"convergence":[35,83],"and":[36,85,113,118,158,169,174,180],"premature":[37],"stagnation":[38],"high-dimensional":[40],"design":[41],"spaces.":[42],"To":[43],"overcome":[44],"these":[45],"limitations,":[46],"this":[47],"study":[48],"proposes":[49],"an":[50],"Enhanced":[51],"Adaptive":[52],"Quantum":[53],"Genetic":[54,132],"Algorithm":[55,133],"(EA-QGA),":[56],"which":[57,135],"integrates":[58],"quantum":[59,69,91,137],"computation":[60],"principles":[61],"with":[62,196],"classical":[63],"evolutionary":[64],"strategies.":[65],"Implemented":[66],"using":[67,102],"true":[68],"gate":[70],"operations":[71],"on":[72,97],"IBM":[73],"Qiskit":[74],"simulators,":[75],"EA-QGA":[77,151],"leverages":[78],"compact":[80],"population,":[81],"rapid":[82],"behavior,":[84],"search":[87],"efficiency":[88],"inherent":[89],"computing.":[92],"framework":[94],"evaluated":[96,163],"three":[98,162],"benchmark":[99],"circuits":[101],"45":[103],"nm":[104],"CMOS":[105],"technology:":[106],"differential":[108],"amplifier,":[109],"two-stage":[111],"OTA,":[112,117],"folded":[115],"cascode":[116],"its":[119],"performance,":[120],"measured":[121],"terms":[123],"figure-of-merit":[125],"(FoM),":[126],"compared":[128],"against":[129],"Quantum-Inspired":[131],"(QIGA),":[134],"simulates":[136],"behavior":[138],"through":[139],"mathematical":[140],"modeling.":[141],"Experimental":[142],"results":[143,184],"show":[144],"that,":[145],"relative":[146],"QIGA,":[148],"proposed":[150,188],"achieves":[152,192],"FoM":[153],"improvements":[154],"0.62%,":[156],"3.33%,":[157],"14.10%":[159],"across":[160],"circuits,":[164],"while":[165],"converging":[166],"4.6\u00d7,":[167],"5.8\u00d7,":[168],"5.6\u00d7":[170],"faster":[171],"generations":[173],"reducing":[175],"runtime":[176],"by":[177],"2.8\u00d7,":[178,179],"2.4\u00d7,":[181],"respectively.":[182],"These":[183],"demonstrate":[185],"that":[186],"EA":[189],"QGA":[190],"consistently":[191],"globally":[193],"optimal":[194],"solutions":[195],"substantially":[197],"improved":[198],"computational":[199],"efficiency,":[200],"making":[201],"it":[202],"promising":[204],"candidate":[205],"for":[206],"high-performance":[207],"IC":[209],"design.":[210]},"counts_by_year":[],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2026-02-01T00:00:00"}