{"id":"https://openalex.org/W7123343464","doi":"https://doi.org/10.1109/access.2026.3653483","title":"Dual-Doped Reconfigurable FETs for Hardware Security: A TCAD Approach","display_name":"Dual-Doped Reconfigurable FETs for Hardware Security: A TCAD Approach","publication_year":2026,"publication_date":"2026-01-01","ids":{"openalex":"https://openalex.org/W7123343464","doi":"https://doi.org/10.1109/access.2026.3653483"},"language":null,"primary_location":{"id":"doi:10.1109/access.2026.3653483","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2026.3653483","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1109/access.2026.3653483","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5122856248","display_name":"Rub\u00e9n Ortega","orcid":null},"institutions":[{"id":"https://openalex.org/I173304897","display_name":"Universidad de Granada","ror":"https://ror.org/04njjy449","country_code":"ES","type":"education","lineage":["https://openalex.org/I173304897"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Rub\u00e9n Ortega","raw_affiliation_strings":["Departamento de Electr&#x00F3;nica y Tecnolog&#x00ED;a de Computadores, Centro de Investigaci&#x00F3;n en Tecnolog&#x00ED;as de la Informaci&#x00F3;n y las Comunicaciones (CITIC), Universidad de Granada, Granada, Spain"],"raw_orcid":"https://orcid.org/0009-0004-6522-8273","affiliations":[{"raw_affiliation_string":"Departamento de Electr&#x00F3;nica y Tecnolog&#x00ED;a de Computadores, Centro de Investigaci&#x00F3;n en Tecnolog&#x00ED;as de la Informaci&#x00F3;n y las Comunicaciones (CITIC), Universidad de Granada, Granada, Spain","institution_ids":["https://openalex.org/I173304897"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5122895880","display_name":"Antonio Herv\u00e1s","orcid":null},"institutions":[{"id":"https://openalex.org/I173304897","display_name":"Universidad de Granada","ror":"https://ror.org/04njjy449","country_code":"ES","type":"education","lineage":["https://openalex.org/I173304897"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Antonio Herv\u00e1s","raw_affiliation_strings":["Departamento de Electr&#x00F3;nica y Tecnolog&#x00ED;a de Computadores, Centro de Investigaci&#x00F3;n en Tecnolog&#x00ED;as de la Informaci&#x00F3;n y las Comunicaciones (CITIC), Universidad de Granada, Granada, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Departamento de Electr&#x00F3;nica y Tecnolog&#x00ED;a de Computadores, Centro de Investigaci&#x00F3;n en Tecnolog&#x00ED;as de la Informaci&#x00F3;n y las Comunicaciones (CITIC), Universidad de Granada, Granada, Spain","institution_ids":["https://openalex.org/I173304897"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5122851073","display_name":"Luca Donetti","orcid":null},"institutions":[{"id":"https://openalex.org/I173304897","display_name":"Universidad de Granada","ror":"https://ror.org/04njjy449","country_code":"ES","type":"education","lineage":["https://openalex.org/I173304897"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Luca Donetti","raw_affiliation_strings":["Departamento de Electr&#x00F3;nica y Tecnolog&#x00ED;a de Computadores, Centro de Investigaci&#x00F3;n en Tecnolog&#x00ED;as de la Informaci&#x00F3;n y las Comunicaciones (CITIC), Universidad de Granada, Granada, Spain"],"raw_orcid":"https://orcid.org/0000-0002-5189-867X","affiliations":[{"raw_affiliation_string":"Departamento de Electr&#x00F3;nica y Tecnolog&#x00ED;a de Computadores, Centro de Investigaci&#x00F3;n en Tecnolog&#x00ED;as de la Informaci&#x00F3;n y las Comunicaciones (CITIC), Universidad de Granada, Granada, Spain","institution_ids":["https://openalex.org/I173304897"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5122908154","display_name":"Alberto Mart\u00ednez","orcid":null},"institutions":[{"id":"https://openalex.org/I173304897","display_name":"Universidad de Granada","ror":"https://ror.org/04njjy449","country_code":"ES","type":"education","lineage":["https://openalex.org/I173304897"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Alberto Mart\u00ednez","raw_affiliation_strings":["Departamento de Electr&#x00F3;nica y Tecnolog&#x00ED;a de Computadores, Centro de Investigaci&#x00F3;n en Tecnolog&#x00ED;as de la Informaci&#x00F3;n y las Comunicaciones (CITIC), Universidad de Granada, Granada, Spain"],"raw_orcid":"https://orcid.org/0009-0000-6027-9216","affiliations":[{"raw_affiliation_string":"Departamento de Electr&#x00F3;nica y Tecnolog&#x00ED;a de Computadores, Centro de Investigaci&#x00F3;n en Tecnolog&#x00ED;as de la Informaci&#x00F3;n y las Comunicaciones (CITIC), Universidad de Granada, Granada, Spain","institution_ids":["https://openalex.org/I173304897"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067913368","display_name":"Carlos M\u00e1rquez","orcid":"https://orcid.org/0000-0003-0159-9951"},"institutions":[{"id":"https://openalex.org/I173304897","display_name":"Universidad de Granada","ror":"https://ror.org/04njjy449","country_code":"ES","type":"education","lineage":["https://openalex.org/I173304897"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Carlos M\u00e1rquez","raw_affiliation_strings":["Departamento de Electr&#x00F3;nica y Tecnolog&#x00ED;a de Computadores, Centro de Investigaci&#x00F3;n en Tecnolog&#x00ED;as de la Informaci&#x00F3;n y las Comunicaciones (CITIC), Universidad de Granada, Granada, Spain"],"raw_orcid":"https://orcid.org/0000-0003-0159-9951","affiliations":[{"raw_affiliation_string":"Departamento de Electr&#x00F3;nica y Tecnolog&#x00ED;a de Computadores, Centro de Investigaci&#x00F3;n en Tecnolog&#x00ED;as de la Informaci&#x00F3;n y las Comunicaciones (CITIC), Universidad de Granada, Granada, Spain","institution_ids":["https://openalex.org/I173304897"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5122869924","display_name":"Manuel Ca\u00f1o-Garc\u00eda","orcid":null},"institutions":[{"id":"https://openalex.org/I173304897","display_name":"Universidad de Granada","ror":"https://ror.org/04njjy449","country_code":"ES","type":"education","lineage":["https://openalex.org/I173304897"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Manuel Ca\u00f1o-Garc\u00eda","raw_affiliation_strings":["Departamento de Electr&#x00F3;nica y Tecnolog&#x00ED;a de Computadores, Centro de Investigaci&#x00F3;n en Tecnolog&#x00ED;as de la Informaci&#x00F3;n y las Comunicaciones (CITIC), Universidad de Granada, Granada, Spain"],"raw_orcid":"https://orcid.org/0000-0002-4437-4296","affiliations":[{"raw_affiliation_string":"Departamento de Electr&#x00F3;nica y Tecnolog&#x00ED;a de Computadores, Centro de Investigaci&#x00F3;n en Tecnolog&#x00ED;as de la Informaci&#x00F3;n y las Comunicaciones (CITIC), Universidad de Granada, Granada, Spain","institution_ids":["https://openalex.org/I173304897"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5122896199","display_name":"Francisco G\u00e1miz","orcid":null},"institutions":[{"id":"https://openalex.org/I173304897","display_name":"Universidad de Granada","ror":"https://ror.org/04njjy449","country_code":"ES","type":"education","lineage":["https://openalex.org/I173304897"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Francisco G\u00e1miz","raw_affiliation_strings":["Departamento de Electr&#x00F3;nica y Tecnolog&#x00ED;a de Computadores, Centro de Investigaci&#x00F3;n en Tecnolog&#x00ED;as de la Informaci&#x00F3;n y las Comunicaciones (CITIC), Universidad de Granada, Granada, Spain"],"raw_orcid":"https://orcid.org/0000-0002-5072-7924","affiliations":[{"raw_affiliation_string":"Departamento de Electr&#x00F3;nica y Tecnolog&#x00ED;a de Computadores, Centro de Investigaci&#x00F3;n en Tecnolog&#x00ED;as de la Informaci&#x00F3;n y las Comunicaciones (CITIC), Universidad de Granada, Granada, Spain","institution_ids":["https://openalex.org/I173304897"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045645277","display_name":"Carlos Navarro","orcid":"https://orcid.org/0000-0002-7846-4599"},"institutions":[{"id":"https://openalex.org/I173304897","display_name":"Universidad de Granada","ror":"https://ror.org/04njjy449","country_code":"ES","type":"education","lineage":["https://openalex.org/I173304897"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Carlos Navarro","raw_affiliation_strings":["Departamento de Electr&#x00F3;nica y Tecnolog&#x00ED;a de Computadores, Centro de Investigaci&#x00F3;n en Tecnolog&#x00ED;as de la Informaci&#x00F3;n y las Comunicaciones (CITIC), Universidad de Granada, Granada, Spain"],"raw_orcid":"https://orcid.org/0000-0002-7846-4599","affiliations":[{"raw_affiliation_string":"Departamento de Electr&#x00F3;nica y Tecnolog&#x00ED;a de Computadores, Centro de Investigaci&#x00F3;n en Tecnolog&#x00ED;as de la Informaci&#x00F3;n y las Comunicaciones (CITIC), Universidad de Granada, Granada, Spain","institution_ids":["https://openalex.org/I173304897"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I173304897"],"apc_list":{"value":2075,"currency":"USD","value_usd":2075},"apc_paid":{"value":2075,"currency":"USD","value_usd":2075},"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.02835148,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"14","issue":null,"first_page":"8366","last_page":"8374"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9786999821662903,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9786999821662903,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.01119999960064888,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.0008999999845400453,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.8716999888420105},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6032000184059143},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5404999852180481},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5131999850273132},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.49799999594688416},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.48019999265670776},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.47209998965263367},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.46880000829696655},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4332999885082245}],"concepts":[{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.8716999888420105},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6710000038146973},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6032000184059143},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5404999852180481},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5131999850273132},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5080000162124634},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.49799999594688416},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.48019999265670776},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.47209998965263367},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.46880000829696655},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4332999885082245},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.42170000076293945},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.41260001063346863},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.40639999508857727},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.39980000257492065},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3774999976158142},{"id":"https://openalex.org/C180405849","wikidata":"https://www.wikidata.org/wiki/Q173464","display_name":"Resistor\u2013transistor logic","level":5,"score":0.37689998745918274},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37470000982284546},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.3434000015258789},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.33709999918937683},{"id":"https://openalex.org/C39217717","wikidata":"https://www.wikidata.org/wiki/Q1432354","display_name":"Hardware security module","level":3,"score":0.32519999146461487},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.32280001044273376},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.31700000166893005},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.311599999666214},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.28529998660087585},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.27959999442100525},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.2703000009059906},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.26089999079704285},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2587999999523163}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/access.2026.3653483","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2026.3653483","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1109/access.2026.3653483","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2026.3653483","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.8293576836585999,"id":"https://metadata.un.org/sdg/16","display_name":"Peace, Justice and strong institutions"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W1524250393","https://openalex.org/W2021433466","https://openalex.org/W2056587731","https://openalex.org/W2063615695","https://openalex.org/W2067276029","https://openalex.org/W2099101940","https://openalex.org/W2116590916","https://openalex.org/W2164152592","https://openalex.org/W2343475170","https://openalex.org/W2419784917","https://openalex.org/W2537886103","https://openalex.org/W2587608034","https://openalex.org/W2587958472","https://openalex.org/W2615060729","https://openalex.org/W2708742051","https://openalex.org/W2741711485","https://openalex.org/W2771999643","https://openalex.org/W2790282160","https://openalex.org/W2806992466","https://openalex.org/W2906629987","https://openalex.org/W2944647304","https://openalex.org/W2963778014","https://openalex.org/W3035438326","https://openalex.org/W3042862317","https://openalex.org/W3140586337","https://openalex.org/W4241041944","https://openalex.org/W4280515648","https://openalex.org/W4309790177","https://openalex.org/W4312100917","https://openalex.org/W4385624862","https://openalex.org/W4390591016","https://openalex.org/W4392214558","https://openalex.org/W4401568830","https://openalex.org/W4414270207"],"related_works":[],"abstract_inverted_index":{"A":[0],"novel":[1],"variant":[2],"of":[3,14],"reconfigurable":[4],"FETs":[5],"(RFETs),":[6],"employing":[7],"source":[8],"and":[9,39,55,63,71,83,90,107,120,140],"drain":[10],"doped":[11],"terminals":[12],"instead":[13],"Schottky":[15],"contacts,":[16],"is":[17,85],"explored":[18],"through":[19,57],"TCAD":[20],"simulations":[21,59],"for":[22,111,137],"implementing":[23],"logic":[24,41],"circuits":[25],"that":[26],"integrate":[27],"Design-for-Trust":[28,138],"(DfTr)":[29],"techniques.":[30],"These":[31],"include":[32],"security":[33,84],"strategies":[34],"such":[35],"as":[36,133,141],"circuit":[37,64,96,147],"camouflaging":[38,70],"advanced":[40],"locking.":[42],"Polymorphic":[43],"Logic":[44],"Gates":[45],"(PLGs)":[46],"based":[47],"on":[48,78],"dual-doped":[49],"RFET":[50],"(DD-RFET)":[51],"technology":[52],"are":[53,76],"designed":[54],"validated":[56],"mixed-mode":[58],"at":[60],"both":[61],"gate":[62],"levels.":[65],"To":[66],"demonstrate":[67],"practical":[68],"applicability,":[69],"an":[72],"URSAT":[73],"logic-locking":[74],"scheme":[75],"implemented":[77],"a":[79,142],"small":[80],"benchmark":[81],"circuit,":[82],"evaluated":[86],"using":[87],"custom":[88],"brute-force":[89],"SAT-like":[91],"attacks.":[92],"While":[93],"the":[94],"limited":[95],"size":[97],"allows":[98],"efficient":[99],"key":[100],"recovery,":[101],"results":[102],"show":[103],"non-trivial":[104],"attack":[105],"effort":[106],"significant":[108],"output":[109],"corruption":[110],"incorrect":[112],"keys.":[113],"In":[114],"addition,":[115],"DD-RFETs":[116],"provide":[117],"enhanced":[118],"reconfigurability":[119],"potentially":[121],"reduced":[122],"transistor":[123],"count":[124],"compared":[125],"to":[126,144],"conventional":[127],"CMOS":[128],"implementations,":[129],"making":[130],"them":[131],"suitable":[132],"complementary":[134],"building":[135],"blocks":[136],"applications":[139],"platform":[143],"explore":[145],"security-oriented":[146],"design.":[148]},"counts_by_year":[],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2026-01-14T00:00:00"}
