{"id":"https://openalex.org/W4417131574","doi":"https://doi.org/10.1109/access.2025.3641762","title":"SHADOWFI: An Open-Source Framework for Fault Evaluation of Complex IC Designs Using Hyperscale Computing","display_name":"SHADOWFI: An Open-Source Framework for Fault Evaluation of Complex IC Designs Using Hyperscale Computing","publication_year":2025,"publication_date":"2025-01-01","ids":{"openalex":"https://openalex.org/W4417131574","doi":"https://doi.org/10.1109/access.2025.3641762"},"language":"en","primary_location":{"id":"doi:10.1109/access.2025.3641762","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2025.3641762","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1109/access.2025.3641762","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046650816","display_name":"Juan-David Guerrero-Balaguera","orcid":"https://orcid.org/0000-0001-6852-2372"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Juan-David Guerrero-Balaguera","raw_affiliation_strings":["Department of Control and Computer Engineering, Politecnico di Torino (DAUIN), Turin, Italy","Department of Control and Computer Engineering (DAUIN), Politecnico di Torino, Turin, Italy"],"raw_orcid":"https://orcid.org/0000-0001-6852-2372","affiliations":[{"raw_affiliation_string":"Department of Control and Computer Engineering, Politecnico di Torino (DAUIN), Turin, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Department of Control and Computer Engineering (DAUIN), Politecnico di Torino, Turin, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006252702","display_name":"Robert Limas Sierra","orcid":"https://orcid.org/0000-0001-5206-3757"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Robert Limas-Sierra","raw_affiliation_strings":["Department of Control and Computer Engineering, Politecnico di Torino (DAUIN), Turin, Italy","Department of Control and Computer Engineering (DAUIN), Politecnico di Torino, Turin, Italy"],"raw_orcid":"https://orcid.org/0000-0001-5206-3757","affiliations":[{"raw_affiliation_string":"Department of Control and Computer Engineering, Politecnico di Torino (DAUIN), Turin, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Department of Control and Computer Engineering (DAUIN), Politecnico di Torino, Turin, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5120725057","display_name":"Oguz Sensoz","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Oguz Sensoz","raw_affiliation_strings":["Department of Control and Computer Engineering, Politecnico di Torino (DAUIN), Turin, Italy","Department of Control and Computer Engineering (DAUIN), Politecnico di Torino, Turin, Italy"],"raw_orcid":"https://orcid.org/0009-0009-1319-9462","affiliations":[{"raw_affiliation_string":"Department of Control and Computer Engineering, Politecnico di Torino (DAUIN), Turin, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Department of Control and Computer Engineering (DAUIN), Politecnico di Torino, Turin, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107558399","display_name":"Josie E. Rodriguez Condia","orcid":"https://orcid.org/0000-0001-5957-5624"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Josie E. Rodriguez Condia","raw_affiliation_strings":["Department of Control and Computer Engineering, Politecnico di Torino (DAUIN), Turin, Italy","Department of Control and Computer Engineering (DAUIN), Politecnico di Torino, Turin, Italy"],"raw_orcid":"https://orcid.org/0000-0001-5957-5624","affiliations":[{"raw_affiliation_string":"Department of Control and Computer Engineering, Politecnico di Torino (DAUIN), Turin, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Department of Control and Computer Engineering (DAUIN), Politecnico di Torino, Turin, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070731381","display_name":"Maynor Giovanni Ballina Escobar","orcid":null},"institutions":[{"id":"https://openalex.org/I12323705","display_name":"The Abdus Salam International Centre for Theoretical Physics (ICTP)","ror":"https://ror.org/009gyvm78","country_code":"IT","type":"facility","lineage":["https://openalex.org/I12323705","https://openalex.org/I1286959531","https://openalex.org/I1293226324","https://openalex.org/I2801247003"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Maynor Giovanni Ballina Escobar","raw_affiliation_strings":["MLab, STI Unit, The Abdus Salam International Centre for Theoretical Physics (ICTP), Trieste, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"MLab, STI Unit, The Abdus Salam International Centre for Theoretical Physics (ICTP), Trieste, Italy","institution_ids":["https://openalex.org/I12323705"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034159452","display_name":"M.L. Crespo","orcid":"https://orcid.org/0000-0002-5483-3388"},"institutions":[{"id":"https://openalex.org/I12323705","display_name":"The Abdus Salam International Centre for Theoretical Physics (ICTP)","ror":"https://ror.org/009gyvm78","country_code":"IT","type":"facility","lineage":["https://openalex.org/I12323705","https://openalex.org/I1286959531","https://openalex.org/I1293226324","https://openalex.org/I2801247003"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Maria Liz Crespo","raw_affiliation_strings":["MLab, STI Unit, The Abdus Salam International Centre for Theoretical Physics (ICTP), Trieste, Italy"],"raw_orcid":"https://orcid.org/0000-0002-5483-3388","affiliations":[{"raw_affiliation_string":"MLab, STI Unit, The Abdus Salam International Centre for Theoretical Physics (ICTP), Trieste, Italy","institution_ids":["https://openalex.org/I12323705"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080786056","display_name":"Sergio Carrato","orcid":"https://orcid.org/0000-0003-2953-8886"},"institutions":[{"id":"https://openalex.org/I142444530","display_name":"University of Trieste","ror":"https://ror.org/02n742c10","country_code":"IT","type":"education","lineage":["https://openalex.org/I142444530"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Sergio Carrato","raw_affiliation_strings":["Dipartimento di Ingegneria e Architettura (DIA), Universita degli Studi di Trieste (UNITS), Trieste, Italy"],"raw_orcid":"https://orcid.org/0000-0003-2953-8886","affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria e Architettura (DIA), Universita degli Studi di Trieste (UNITS), Trieste, Italy","institution_ids":["https://openalex.org/I142444530"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058555274","display_name":"M. Sonza Reorda","orcid":"https://orcid.org/0000-0003-2899-7669"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Matteo Sonza Reorda","raw_affiliation_strings":["Department of Control and Computer Engineering, Politecnico di Torino (DAUIN), Turin, Italy","Department of Control and Computer Engineering (DAUIN), Politecnico di Torino, Turin, Italy"],"raw_orcid":"https://orcid.org/0000-0003-2899-7669","affiliations":[{"raw_affiliation_string":"Department of Control and Computer Engineering, Politecnico di Torino (DAUIN), Turin, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Department of Control and Computer Engineering (DAUIN), Politecnico di Torino, Turin, Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":1850,"currency":"USD","value_usd":1850},"apc_paid":{"value":1850,"currency":"USD","value_usd":1850},"fwci":1.0286,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.81458564,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":"13","issue":null,"first_page":"211382","last_page":"211406"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.6818000078201294,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.6818000078201294,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.15479999780654907,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.05460000038146973,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.8759999871253967},{"id":"https://openalex.org/keywords/hardware-emulation","display_name":"Hardware emulation","score":0.7451000213623047},{"id":"https://openalex.org/keywords/fault-injection","display_name":"Fault injection","score":0.7055000066757202},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5888000130653381},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5831000208854675},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5723999738693237},{"id":"https://openalex.org/keywords/workflow","display_name":"Workflow","score":0.5527999997138977},{"id":"https://openalex.org/keywords/usability","display_name":"Usability","score":0.5174999833106995}],"concepts":[{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.8759999871253967},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7986000180244446},{"id":"https://openalex.org/C94115699","wikidata":"https://www.wikidata.org/wiki/Q5656406","display_name":"Hardware emulation","level":3,"score":0.7451000213623047},{"id":"https://openalex.org/C2775928411","wikidata":"https://www.wikidata.org/wiki/Q2041312","display_name":"Fault injection","level":3,"score":0.7055000066757202},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6148999929428101},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5888000130653381},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5831000208854675},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5723999738693237},{"id":"https://openalex.org/C177212765","wikidata":"https://www.wikidata.org/wiki/Q627335","display_name":"Workflow","level":2,"score":0.5527999997138977},{"id":"https://openalex.org/C170130773","wikidata":"https://www.wikidata.org/wiki/Q216378","display_name":"Usability","level":2,"score":0.5174999833106995},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.49320000410079956},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.46480000019073486},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.44519999623298645},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43619999289512634},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.42309999465942383},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.3977999985218048},{"id":"https://openalex.org/C167391956","wikidata":"https://www.wikidata.org/wiki/Q1401211","display_name":"Fault model","level":3,"score":0.39500001072883606},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.39329999685287476},{"id":"https://openalex.org/C50712370","wikidata":"https://www.wikidata.org/wiki/Q4269346","display_name":"Software fault tolerance","level":3,"score":0.3928999900817871},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.37610000371932983},{"id":"https://openalex.org/C77019957","wikidata":"https://www.wikidata.org/wiki/Q2689057","display_name":"Dependability","level":2,"score":0.3481000065803528},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3287000060081482},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.3116999864578247},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.2565999925136566},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.2506999969482422}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/access.2025.3641762","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2025.3641762","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},{"id":"pmh:oai:arts.units.it:11368/3138239","is_oa":false,"landing_page_url":"https://hdl.handle.net/11368/3138239","pdf_url":null,"source":{"id":"https://openalex.org/S4306400480","display_name":"ArTS Archivio della ricerca di Trieste (University of Trieste https://www.units.it/)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I142444530","host_organization_name":"University of Trieste","host_organization_lineage":["https://openalex.org/I142444530"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:doaj.org/article:05a5fafc25d2442db43df9b0b62d92b4","is_oa":true,"landing_page_url":"https://doaj.org/article/05a5fafc25d2442db43df9b0b62d92b4","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Access, Vol 13, Pp 211382-211406 (2025)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1109/access.2025.3641762","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2025.3641762","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Cutting-edge":[0],"integrated":[1],"circuits":[2],"(ICs)":[3],"are":[4,78],"increasingly":[5],"vulnerable":[6],"to":[7,23,29,38,110,118],"hardware":[8,31],"faults,":[9],"which":[10,101,161,173],"can":[11,36],"jeopardize":[12],"the":[13,17,25,44,55,86,103,111,115,139,163,175],"overall":[14],"reliability":[15,149],"of":[16,27,58,76,89,96,105,142,151,165,177,204],"system.":[18],"Hence,":[19],"it":[20],"is":[21,99,217],"crucial":[22],"evaluate":[24],"impact":[26],"faults":[28],"identify":[30],"vulnerabilities":[32],"that":[33,137],"later":[34],"designers":[35],"use":[37],"devise":[39],"fault":[40,59,106,134,146,213],"mitigation":[41],"solutions":[42],"during":[43],"circuit":[45],"design":[46,206],"stages.":[47],"Fault":[48],"injection":[49],"(FI)":[50],"through":[51],"in-circuit":[52],"emulation":[53,64,107,135],"tackles":[54],"inherent":[56,112],"complexity":[57,88,113],"evaluations":[60],"by":[61],"adopting":[62],"FPGA":[63,178],"strategies.":[65],"Although":[66],"various":[67],"works":[68],"report":[69,190],"frameworks":[70,98],"using":[71],"this":[72],"FI":[73,123,166,186],"approach,":[74],"most":[75],"them":[77],"technology-dependent":[79],"and":[80,114,132,148,189,211],"hardly":[81],"scalable":[82],"when":[83],"dealing":[84],"with":[85],"increasing":[87],"modern":[90],"IC":[91,153,205],"architectures.":[92],"In":[93],"addition,":[94],"none":[95],"these":[97],"disclosed,":[100],"limits":[102],"adoption":[104],"strategies":[108],"due":[109],"required":[116],"time":[117],"set":[119,203],"up":[120],"a":[121,129,202],"functional":[122,159],"environment.":[124],"This":[125],"work":[126],"introduces":[127],"SHADOWFI,":[128],"generic,":[130],"open-source,":[131],"netlist-based":[133],"framework":[136,182],"leverages":[138,174],"computational":[140],"capabilities":[141],"hyperscale":[143],"infrastructures":[144],"for":[145],"characterization":[147],"estimation":[150],"complex":[152],"designs.":[154],"SHADOWFI":[155,197,216],"offers":[156],"two":[157],"different":[158],"workflows:i)simulation,":[160],"enables":[162],"parallelization":[164],"tasks":[167],"on":[168,201],"high-performance":[169],"computing":[170],"systems,":[171],"andii)emulation,":[172],"flexibility":[176],"cluster":[179],"implementations.":[180],"The":[181],"automates":[183],"saboteur":[184],"insertion,":[185],"campaign":[187],"execution,":[188],"generation,":[191],"requiring":[192],"minimal":[193],"user":[194],"configuration.":[195],"Each":[196],"workflow":[198],"was":[199],"evaluated":[200],"benchmarks,":[207],"demonstrating":[208],"practical":[209],"usability":[210],"significant":[212],"injections":[214],"speedup.":[215],"publicly":[218],"available":[219],"at":[220],"https://github.com/divadnauj-GB/SHADOWFI.git.":[221]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-07-29T09:40:50.615796","created_date":"2025-12-08T00:00:00"}