{"id":"https://openalex.org/W4416286259","doi":"https://doi.org/10.1109/access.2025.3633942","title":"Compilation Framework for Dynamically Reconfigurable Array Architectures","display_name":"Compilation Framework for Dynamically Reconfigurable Array Architectures","publication_year":2025,"publication_date":"2025-01-01","ids":{"openalex":"https://openalex.org/W4416286259","doi":"https://doi.org/10.1109/access.2025.3633942"},"language":"en","primary_location":{"id":"doi:10.1109/access.2025.3633942","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2025.3633942","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1109/access.2025.3633942","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015127480","display_name":"Anish Vipperla","orcid":"https://orcid.org/0000-0002-8160-6367"},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Anish Vipperla","raw_affiliation_strings":["Arizona State University, Tempe, AZ, USA"],"affiliations":[{"raw_affiliation_string":"Arizona State University, Tempe, AZ, USA","institution_ids":["https://openalex.org/I55732556"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008940282","display_name":"N. S. Sakthivel Murugan","orcid":"https://orcid.org/0009-0000-1613-8811"},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Narayanan Murugan","raw_affiliation_strings":["Arizona State University, Tempe, AZ, USA"],"affiliations":[{"raw_affiliation_string":"Arizona State University, Tempe, AZ, USA","institution_ids":["https://openalex.org/I55732556"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080974820","display_name":"Ali Akoglu","orcid":"https://orcid.org/0000-0001-7982-8991"},"institutions":[{"id":"https://openalex.org/I138006243","display_name":"University of Arizona","ror":"https://ror.org/03m2x1q45","country_code":"US","type":"education","lineage":["https://openalex.org/I138006243"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ali Akoglu","raw_affiliation_strings":["The University of Arizona, Tucson, AZ, USA"],"affiliations":[{"raw_affiliation_string":"The University of Arizona, Tucson, AZ, USA","institution_ids":["https://openalex.org/I138006243"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025336372","display_name":"Chaitali Chakrabarti","orcid":"https://orcid.org/0000-0002-9859-7778"},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chaitali Chakrabarti","raw_affiliation_strings":["Arizona State University, Tempe, AZ, USA"],"affiliations":[{"raw_affiliation_string":"Arizona State University, Tempe, AZ, USA","institution_ids":["https://openalex.org/I55732556"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5015127480"],"corresponding_institution_ids":["https://openalex.org/I55732556"],"apc_list":{"value":1850,"currency":"USD","value_usd":1850},"apc_paid":{"value":1850,"currency":"USD","value_usd":1850},"fwci":2.1983,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.90245919,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":98},"biblio":{"volume":"13","issue":null,"first_page":"196415","last_page":"196432"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.8953999876976013,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.8953999876976013,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.09049999713897705,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.0020000000949949026,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.8676999807357788},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5587000250816345},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.4616999924182892},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.41850000619888306},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.39430001378059387},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.3788999915122986},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.3628999888896942},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.35920000076293945},{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"Instruction scheduling","score":0.32839998602867126}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8833000063896179},{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.8676999807357788},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5745000243186951},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5587000250816345},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5455999970436096},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.4616999924182892},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.41850000619888306},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40130001306533813},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.39430001378059387},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.3788999915122986},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.3628999888896942},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.35920000076293945},{"id":"https://openalex.org/C73564150","wikidata":"https://www.wikidata.org/wiki/Q11417093","display_name":"Instruction scheduling","level":5,"score":0.32839998602867126},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.31439998745918274},{"id":"https://openalex.org/C139352143","wikidata":"https://www.wikidata.org/wiki/Q82571","display_name":"Linear algebra","level":2,"score":0.31130000948905945},{"id":"https://openalex.org/C2778545087","wikidata":"https://www.wikidata.org/wiki/Q4795883","display_name":"Array processing","level":4,"score":0.3034999966621399},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.3009999990463257},{"id":"https://openalex.org/C188854837","wikidata":"https://www.wikidata.org/wiki/Q268469","display_name":"Software pipelining","level":3,"score":0.2854999899864197},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.28060001134872437},{"id":"https://openalex.org/C161824985","wikidata":"https://www.wikidata.org/wiki/Q919509","display_name":"Vector processor","level":2,"score":0.28049999475479126},{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.27810001373291016},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.2766999900341034},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2718000113964081},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.26429998874664307},{"id":"https://openalex.org/C88468194","wikidata":"https://www.wikidata.org/wiki/Q1172416","display_name":"Data-flow analysis","level":3,"score":0.26409998536109924},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.2624000012874603}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/access.2025.3633942","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2025.3633942","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:b958e2c619b644d489dc0203e9b09d9f","is_oa":true,"landing_page_url":"https://doaj.org/article/b958e2c619b644d489dc0203e9b09d9f","pdf_url":null,"source":{"id":"https://openalex.org/S112646816","display_name":"SHILAP Revista de lepidopterolog\u00eda","issn_l":"0300-5267","issn":["0300-5267","2340-4078"],"is_oa":true,"is_in_doaj":true,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Access, Vol 13, Pp 196415-196432 (2025)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1109/access.2025.3633942","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2025.3633942","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G599699146","display_name":null,"funder_award_id":"FA8650-18-2-7860","funder_id":"https://openalex.org/F4320332180","funder_display_name":"Defense Advanced Research Projects Agency"},{"id":"https://openalex.org/G647044356","display_name":null,"funder_award_id":"FA8650-18-2-7860","funder_id":"https://openalex.org/F4320338294","funder_display_name":"Air Force Research Laboratory"}],"funders":[{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"},{"id":"https://openalex.org/F4320338294","display_name":"Air Force Research Laboratory","ror":"https://ror.org/02e2egq70"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,71,78,111,148,188],"compilation":[4,189],"and":[5,36,77,110,141,165,176,204],"scheduling":[6,177],"framework":[7,22],"for":[8,23,33,138,191,211],"high-performance":[9],"mapping":[10,175],"of":[11,46,49,60,64,124,153,173,202],"computationally-intensive":[12],"kernels":[13],"on":[14],"Dynamically":[15],"Reconfigurable":[16],"Array":[17],"Architectures.":[18],"We":[19,69],"showcase":[20],"the":[21,94,125,159,162,171],"Domain":[24],"Adaptive":[25],"Processor":[26],"(DAP)":[27],"-":[28],"an":[29,47,103,130,198],"array":[30,48,194],"accelerator":[31],"designed":[32],"signal":[34,142],"processing":[35,143],"communication":[37],"workloads":[38],"that":[39,92,150],"has":[40],"near-ASIC":[41],"energy":[42],"efficiency.":[43],"DAP":[44],"consists":[45,59],"homogeneous":[50],"Processing":[51],"Element":[52],"(PE)":[53],"clusters,":[54],"where":[55],"each":[56],"PE":[57,115],"cluster":[58],"heterogeneous":[61],"PEs":[62],"capable":[63,152],"executing":[65],"Very-Long-Instruction-Word":[66],"(VLIW)":[67],"instructions.":[68],"introduce":[70],"virtual":[72],"Instruction":[73],"Set":[74],"Architecture":[75],"(ISA)":[76],"sequential":[79],"assembly":[80],"to":[81,136,197],"low-level":[82,95,208],"micro-code":[83,96],"conversion":[84],"mechanism.":[85],"The":[86],"proposed":[87],"work":[88],"includes":[89],"optimization":[90],"techniques":[91],"transform":[93],"into":[97],"compact":[98],"VLIW":[99,126],"instructions":[100],"resulting":[101,128],"in":[102,114,129,132,180,200],"average":[104],"instruction":[105],"count":[106],"reduction":[107],"by":[108,134],"1.8x":[109],"significant":[112],"increase":[113],"utilization.":[116],"In":[117],"addition,":[118],"we":[119,146],"demonstrate":[120],"rate-aware":[121],"software-based":[122],"pipelining":[123],"code":[127],"improvement":[131,199],"throughput":[133],"up":[135],"15x":[137],"linear":[139],"algebra":[140],"kernels.":[144],"Further,":[145],"propose":[147],"scheduler":[149],"is":[151],"automatically":[154],"resolving":[155],"data":[156],"dependencies":[157],"between":[158],"threads":[160],"at":[161],"micro-instruction":[163],"level":[164],"accurately":[166],"schedule":[167],"custom":[168],"dataflows":[169],"overcoming":[170],"limitations":[172],"fixed":[174],"schemes":[178],"used":[179],"traditional":[181],"CGRA":[182],"compilers.":[183],"These":[184],"contributions":[185],"together,":[186],"provide":[187],"flow":[190],"dynamically":[192],"reconfigurable":[193],"architectures":[195],"leading":[196],"ease":[201],"programmability":[203],"productivity":[205],"while":[206],"ensuring":[207],"implementation":[209],"flexibility":[210],"performance-critical":[212],"applications.":[213]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2025-11-17T00:00:00"}