{"id":"https://openalex.org/W4411231969","doi":"https://doi.org/10.1109/access.2025.3579294","title":"System Verification and FPGA Implementation of Hardware Preemptive Scheduler for RISC-V Processor","display_name":"System Verification and FPGA Implementation of Hardware Preemptive Scheduler for RISC-V Processor","publication_year":2025,"publication_date":"2025-01-01","ids":{"openalex":"https://openalex.org/W4411231969","doi":"https://doi.org/10.1109/access.2025.3579294"},"language":"en","primary_location":{"id":"doi:10.1109/access.2025.3579294","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2025.3579294","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1109/access.2025.3579294","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034263055","display_name":"Ionel Zagan","orcid":"https://orcid.org/0000-0003-1322-4516"},"institutions":[{"id":"https://openalex.org/I12012874","display_name":"\u015etefan cel Mare University of Suceava","ror":"https://ror.org/035pkj773","country_code":"RO","type":"education","lineage":["https://openalex.org/I12012874"]}],"countries":["RO"],"is_corresponding":false,"raw_author_name":"Ionel Zagan","raw_affiliation_strings":["PDADMCPI Laboratory, MANSiD Research Center, Stefan cel Mare University of Suceava, Suceava, Romania","Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University, Suceava, Romania"],"raw_orcid":"https://orcid.org/0000-0003-1322-4516","affiliations":[{"raw_affiliation_string":"PDADMCPI Laboratory, MANSiD Research Center, Stefan cel Mare University of Suceava, Suceava, Romania","institution_ids":["https://openalex.org/I12012874"]},{"raw_affiliation_string":"Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University, Suceava, Romania","institution_ids":["https://openalex.org/I12012874"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007053778","display_name":"Vasile Gheorghi\u0163\u0103 G\u0103itan","orcid":"https://orcid.org/0000-0001-9899-5111"},"institutions":[{"id":"https://openalex.org/I12012874","display_name":"\u015etefan cel Mare University of Suceava","ror":"https://ror.org/035pkj773","country_code":"RO","type":"education","lineage":["https://openalex.org/I12012874"]}],"countries":["RO"],"is_corresponding":false,"raw_author_name":"Vasile Gheorghi\u0163\u0103 G\u0103itan","raw_affiliation_strings":["PDADMCPI Laboratory, MANSiD Research Center, Stefan cel Mare University of Suceava, Suceava, Romania","Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University, Suceava, Romania"],"raw_orcid":"https://orcid.org/0000-0001-9899-5111","affiliations":[{"raw_affiliation_string":"PDADMCPI Laboratory, MANSiD Research Center, Stefan cel Mare University of Suceava, Suceava, Romania","institution_ids":["https://openalex.org/I12012874"]},{"raw_affiliation_string":"Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University, Suceava, Romania","institution_ids":["https://openalex.org/I12012874"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I12012874"],"apc_list":{"value":1850,"currency":"USD","value_usd":1850},"apc_paid":{"value":1850,"currency":"USD","value_usd":1850},"fwci":1.377,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.77803405,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":"13","issue":null,"first_page":"103019","last_page":"103032"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9696999788284302,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9605000019073486,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8097002506256104},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7380269765853882},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.7051151990890503},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5406394600868225},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3975936770439148},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3481452465057373},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33473172783851624},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.320782870054245},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.2901507019996643}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8097002506256104},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7380269765853882},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.7051151990890503},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5406394600868225},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3975936770439148},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3481452465057373},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33473172783851624},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.320782870054245},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.2901507019996643}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/access.2025.3579294","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2025.3579294","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:1bc33bee5b9a423d8066d2622806adc4","is_oa":true,"landing_page_url":"https://doaj.org/article/1bc33bee5b9a423d8066d2622806adc4","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Access, Vol 13, Pp 103019-103032 (2025)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1109/access.2025.3579294","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2025.3579294","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.550000011920929,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W2001326614","https://openalex.org/W2034546977","https://openalex.org/W2076947091","https://openalex.org/W2099071274","https://openalex.org/W2127000736","https://openalex.org/W2142256005","https://openalex.org/W2307107752","https://openalex.org/W2539868067","https://openalex.org/W2945385838","https://openalex.org/W2980002395","https://openalex.org/W2984220050","https://openalex.org/W3089200294","https://openalex.org/W3092499535","https://openalex.org/W3133527008","https://openalex.org/W3145794024","https://openalex.org/W3153208734","https://openalex.org/W3183374399","https://openalex.org/W3198861702","https://openalex.org/W3211218493","https://openalex.org/W3212353174","https://openalex.org/W4200045407","https://openalex.org/W4283731542","https://openalex.org/W4364321899","https://openalex.org/W4387587494","https://openalex.org/W4392449541","https://openalex.org/W6601056741"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2035206467","https://openalex.org/W2512308948","https://openalex.org/W2068921804"],"abstract_inverted_index":{"In":[0],"soft-core":[1,129,146],"processor":[2,35,113],"implementations":[3],"based":[4,74],"on":[5,75,106],"software":[6],"schedulers,":[7],"there":[8],"is":[9,65,85,142,181],"an":[10,48,53],"overhead":[11],"that":[12,212],"should":[13],"not":[14,132],"be":[15],"neglected":[16],"in":[17,87,111,126,189,219],"HARD":[18],"and":[19,36,169,198,226],"FIRM":[20],"real-time":[21,261],"systems":[22],"(RTS).":[23],"Due":[24],"to":[25,66,92,99,240],"interrupt":[26],"service":[27],"routines":[28],"(ISRs),":[29],"which":[30],"are":[31],"asynchronous":[32,54],"with":[33,144],"the":[34,44,68,76,82,96,101,107,112,115,127,153,170,194,199,213,222,230,247,251,260,265],"have":[37,254],"a":[38,184],"higher":[39,217,235],"priority":[40,195],"than":[41,135],"thread":[42,50,124],"execution,":[43],"response":[45,224,263],"time":[46,225],"of":[47,62,109,172,201,221,264],"execution":[49,93,103,252],"interrupted":[51],"by":[52,183],"ISR":[55],"may":[56],"exhibit":[57],"jitter.":[58],"The":[59,139,175,209,243],"overall":[60],"purpose":[61],"this":[63,179],"paper":[64],"present":[67],"hardware":[69,256],"scheduler":[70,167],"accelerator":[71],"(HwSA)":[72],"concept":[73],"RISC-V":[77,202],"4-stage":[78],"pipeline":[79,116,173],"CPU,":[80],"where":[81],"scheduling":[83,186],"algorithm":[84,187],"implemented":[86,188],"hardware.":[88],"Assigning":[89],"external":[90],"events":[91],"threads,":[94],"allows":[95],"application":[97],"manager":[98],"improve":[100],"CPU":[102,130],"behavior.":[104],"Based":[105],"multiplication":[108],"resources":[110,158],"datapath,":[114],"registers":[117],"store":[118],"information":[119],"for":[120,160,192,229],"each":[121],"thread.":[122],"Switching":[123],"contexts":[125],"proposed":[128,140,214,248],"does":[131],"require":[133],"more":[134],"1-2":[136],"clock":[137],"cycles.":[138],"system":[141,215],"compared":[143,239],"existing":[145,241],"processors":[147],"using":[148],"different":[149],"parameters,":[150],"such":[151],"as":[152,232,234],"field-programmable":[154],"gate":[155],"arrays":[156],"(FPGA)":[157],"used":[159],"implementation,":[161],"frequency,":[162],"instruction":[163],"set":[164],"architecture":[165],"(ISA),":[166],"type,":[168],"number":[171],"stages.":[174],"scientific":[176],"contribution":[177],"within":[178],"project":[180],"given":[182],"dynamic":[185],"hardware,":[190],"support":[191],"resolving":[193],"inversion":[196],"situations":[197],"use":[200],"ISA":[203],"provided":[204],"under":[205],"open":[206],"source":[207],"licenses.":[208],"analysis":[210],"shows":[211],"has":[216],"performance":[218],"terms":[220],"event":[223],"lower":[227],"jitter":[228],"scheduler,":[231],"well":[233],"FPGA":[236],"resource":[237],"utilization":[238],"designs.":[242],"results":[244],"obtained":[245],"achieve":[246],"objectives":[249],"since":[250],"threads":[253],"their":[255],"context,":[257],"mainly":[258],"following":[259],"deterministic":[262],"system.":[266]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
