{"id":"https://openalex.org/W4390205290","doi":"https://doi.org/10.1109/access.2024.3520877","title":"Fail-Safe Logic Design Strategies Within Modern FPGA Architectures","display_name":"Fail-Safe Logic Design Strategies Within Modern FPGA Architectures","publication_year":2025,"publication_date":"2025-01-01","ids":{"openalex":"https://openalex.org/W4390205290","doi":"https://doi.org/10.1109/access.2024.3520877"},"language":"en","primary_location":{"id":"doi:10.1109/access.2024.3520877","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2024.3520877","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1109/access.2024.3520877","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5115806856","display_name":"Priya A. Bhakta","orcid":"https://orcid.org/0009-0007-3402-2776"},"institutions":[{"id":"https://openalex.org/I169521973","display_name":"University of New Mexico","ror":"https://ror.org/05fs6jp91","country_code":"US","type":"education","lineage":["https://openalex.org/I169521973"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Priya A. Bhakta","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of New Mexico, Albuquerque, NM, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of New Mexico, Albuquerque, NM, USA","institution_ids":["https://openalex.org/I169521973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029774084","display_name":"Jim Plusquellic","orcid":"https://orcid.org/0000-0002-1876-117X"},"institutions":[{"id":"https://openalex.org/I169521973","display_name":"University of New Mexico","ror":"https://ror.org/05fs6jp91","country_code":"US","type":"education","lineage":["https://openalex.org/I169521973"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jim Plusquellic","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of New Mexico, Albuquerque, NM, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of New Mexico, Albuquerque, NM, USA","institution_ids":["https://openalex.org/I169521973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080719673","display_name":"Andrew Suchanek","orcid":"https://orcid.org/0000-0002-9397-2604"},"institutions":[{"id":"https://openalex.org/I4210104735","display_name":"Sandia National Laboratories","ror":"https://ror.org/01apwpt12","country_code":"US","type":"facility","lineage":["https://openalex.org/I1330989302","https://openalex.org/I198811213","https://openalex.org/I4210104735"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andrew Suchanek","raw_affiliation_strings":["Sandia National Laboratories, Albuquerque, NM, USA"],"affiliations":[{"raw_affiliation_string":"Sandia National Laboratories, Albuquerque, NM, USA","institution_ids":["https://openalex.org/I4210104735"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074967265","display_name":"Tom J. Mannos","orcid":"https://orcid.org/0000-0002-1051-473X"},"institutions":[{"id":"https://openalex.org/I4210104735","display_name":"Sandia National Laboratories","ror":"https://ror.org/01apwpt12","country_code":"US","type":"facility","lineage":["https://openalex.org/I1330989302","https://openalex.org/I198811213","https://openalex.org/I4210104735"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tom J. Mannos","raw_affiliation_strings":["Sandia National Laboratories, Albuquerque, NM, USA"],"affiliations":[{"raw_affiliation_string":"Sandia National Laboratories, Albuquerque, NM, USA","institution_ids":["https://openalex.org/I4210104735"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5115806856"],"corresponding_institution_ids":["https://openalex.org/I169521973"],"apc_list":{"value":1850,"currency":"USD","value_usd":1850},"apc_paid":{"value":1850,"currency":"USD","value_usd":1850},"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.00010356,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"13","issue":null,"first_page":"3434","last_page":"3452"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6129895448684692},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5714027285575867},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5652248859405518},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4399092495441437},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4216769337654114},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2765159606933594}],"concepts":[{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6129895448684692},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5714027285575867},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5652248859405518},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4399092495441437},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4216769337654114},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2765159606933594},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/access.2024.3520877","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2024.3520877","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},{"id":"pmh:oai:digitalrepository.unm.edu:ece_etds-1762","is_oa":false,"landing_page_url":"https://digitalrepository.unm.edu/ece_etds/711","pdf_url":null,"source":{"id":"https://openalex.org/S4377196368","display_name":"UNM\u2019s Digital Repository (University of New Mexico)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I169521973","host_organization_name":"University of New Mexico","host_organization_lineage":["https://openalex.org/I169521973"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Electrical and Computer Engineering ETDs","raw_type":"text"},{"id":"pmh:oai:doaj.org/article:973a640741d84956bfe1422579734a47","is_oa":true,"landing_page_url":"https://doaj.org/article/973a640741d84956bfe1422579734a47","pdf_url":null,"source":{"id":"https://openalex.org/S112646816","display_name":"SHILAP Revista de lepidopterolog\u00eda","issn_l":"0300-5267","issn":["0300-5267","2340-4078"],"is_oa":true,"is_in_doaj":true,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Access, Vol 13, Pp 3434-3452 (2025)","raw_type":"article"},{"id":"pmh:oai:osti.gov:2005338","is_oa":true,"landing_page_url":"https://www.osti.gov/biblio/2005338","pdf_url":null,"source":{"id":"https://openalex.org/S4306402487","display_name":"OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I139351228","host_organization_name":"Office of Scientific and Technical Information","host_organization_lineage":["https://openalex.org/I139351228"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null}],"best_oa_location":{"id":"doi:10.1109/access.2024.3520877","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2024.3520877","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.44999998807907104,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1598941862","https://openalex.org/W1964218206","https://openalex.org/W1970885193","https://openalex.org/W1982350175","https://openalex.org/W2005602803","https://openalex.org/W2131221147","https://openalex.org/W2158724905","https://openalex.org/W2587673885","https://openalex.org/W2608632610","https://openalex.org/W2763802695","https://openalex.org/W2943050732","https://openalex.org/W2946945802","https://openalex.org/W2951981700","https://openalex.org/W2988212920","https://openalex.org/W3027559990","https://openalex.org/W3186013935","https://openalex.org/W4237252402","https://openalex.org/W4240833370"],"related_works":["https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2019936863","https://openalex.org/W1996820488","https://openalex.org/W1748531671"],"abstract_inverted_index":{"Fail-safe":[0,169],"computing":[1,4],"refers":[2],"to":[3,8,147],"systems":[5,172],"that":[6],"revert":[7],"a":[9,14,22,51,117],"non-operational":[10],"safe":[11],"state":[12],"when":[13],"fault":[15,34,61,90,154,157,189],"occurs.":[16],"In":[17],"this":[18],"paper,":[19],"we":[20],"investigate":[21],"circuit":[23,113,163],"level":[24],"technique":[25,49,165],"as":[26,50,194],"mitigation":[27],"for":[28,54,168],"single":[29],"event":[30],"upsets":[31],"(SEUs)":[32],"and":[33,43,70,87,124,135,156,178,196],"injection":[35,91,190],"attacks":[36],"on":[37,93],"field":[38],"programmable":[39,71],"gate":[40],"arrays":[41],"(FPGAs),":[42],"analyze":[44],"the":[45,48,140,143,186],"effectiveness":[46],"of":[47,60,121,142,188],"fail-safe":[52,109,148,162],"monitor":[53],"an":[55,78,83,94],"encryption":[56],"algorithm.":[57],"The":[58,96,127,176],"propagation":[59,158],"effects":[62],"through":[63],"FPGA":[64,79,198],"primitives":[65],"including":[66],"lookup":[67],"tables":[68],"(LUTs)":[69],"interconnect":[72],"points":[73],"(PIPs)":[74],"is":[75,174],"assessed":[76],"within":[77,102,139],"architecture":[80],"created":[81],"using":[82,89],"open":[84],"source":[85],"tool,":[86],"validated":[88],"experiments":[92,191],"FPGA.":[95],"analysis":[97],"reveals":[98],"additional":[99,153],"vulnerabilities":[100],"exist":[101],"reconfigurable":[103],"architectures":[104],"over":[105],"those":[106],"in":[107,170,185,197],"equivalent":[108],"application":[110],"specific":[111],"integrated":[112],"(ASIC),":[114],"thus":[115],"requiring":[116],"more":[118],"elaborate":[119],"network":[120],"redundant":[122],"circuits":[123],"checking":[125],"logic.":[126],"configuration":[128],"memory":[129],"bits":[130],"(CMBs),":[131],"which":[132],"configure":[133],"routing":[134],"designate":[136],"logic":[137],"functions":[138],"LUTs":[141],"FPGA,":[144],"add":[145],"complexity":[146],"design":[149,164],"strategies":[150],"by":[151],"introducing":[152],"conditions":[155],"paths.":[159],"A":[160],"resource-efficient":[161],"called":[166],"DEsign":[167],"reCONfigurable":[171],"(DEFCON)":[173],"proposed.":[175],"benefits":[177],"limitations":[179],"associated":[180],"with":[181],"DEFCON":[182],"are":[183],"described":[184],"context":[187],"carried":[192],"out":[193],"simulations":[195],"hardware.":[199]},"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
