{"id":"https://openalex.org/W4400275668","doi":"https://doi.org/10.1109/access.2024.3422802","title":"A Novel Digital Equalizer Based on RF Sampling Beyond GHz","display_name":"A Novel Digital Equalizer Based on RF Sampling Beyond GHz","publication_year":2024,"publication_date":"2024-01-01","ids":{"openalex":"https://openalex.org/W4400275668","doi":"https://doi.org/10.1109/access.2024.3422802"},"language":"en","primary_location":{"id":"doi:10.1109/access.2024.3422802","is_oa":true,"landing_page_url":"http://dx.doi.org/10.1109/access.2024.3422802","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"http://dx.doi.org/10.1109/access.2024.3422802","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055130345","display_name":"Lorenzo Canese","orcid":"https://orcid.org/0000-0002-7859-5150"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Lorenzo Canese","raw_affiliation_strings":["Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028297120","display_name":"G.C. Cardarilli","orcid":"https://orcid.org/0000-0002-7444-876X"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gian Carlo Cardarilli","raw_affiliation_strings":["Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy"],"raw_orcid":"https://orcid.org/0000-0002-7444-876X","affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5093362636","display_name":"Riccardo La Cesa","orcid":"https://orcid.org/0009-0001-4978-4921"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Riccardo la Cesa","raw_affiliation_strings":["Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy"],"raw_orcid":"https://orcid.org/0009-0001-4978-4921","affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063300969","display_name":"Luca Di Nunzio","orcid":"https://orcid.org/0000-0002-4312-7939"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Di Nunzio","raw_affiliation_strings":["Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy"],"raw_orcid":"https://orcid.org/0000-0002-4312-7939","affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048482308","display_name":"Rocco Fazzolari","orcid":"https://orcid.org/0000-0002-7383-2663"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Rocco Fazzolari","raw_affiliation_strings":["Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy"],"raw_orcid":"https://orcid.org/0000-0002-7383-2663","affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075532616","display_name":"Daniele Giardino","orcid":"https://orcid.org/0000-0002-8512-2351"},"institutions":[{"id":"https://openalex.org/I4210103492","display_name":"Advanced Computer System (Italy)","ror":"https://ror.org/018mrwd51","country_code":"IT","type":"company","lineage":["https://openalex.org/I4210103492"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Daniele Giardino","raw_affiliation_strings":["IT Systems Srl, Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IT Systems Srl, Rome, Italy","institution_ids":["https://openalex.org/I4210103492"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000963583","display_name":"M. Re","orcid":"https://orcid.org/0000-0001-9046-1318"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Re","raw_affiliation_strings":["Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy"],"raw_orcid":"https://orcid.org/0000-0001-9046-1318","affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044774713","display_name":"Sergio Span\u00f2","orcid":"https://orcid.org/0000-0002-8230-7211"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Sergio Span\u00f2","raw_affiliation_strings":["Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy"],"raw_orcid":"https://orcid.org/0000-0002-8230-7211","affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Tor Vergata University of Rome, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":1850,"currency":"USD","value_usd":1850},"apc_paid":{"value":1850,"currency":"USD","value_usd":1850},"fwci":3.1441,"has_fulltext":false,"cited_by_count":23,"citation_normalized_percentile":{"value":0.92121431,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":95,"max":99},"biblio":{"volume":"12","issue":null,"first_page":"92560","last_page":"92572"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11248","display_name":"Advanced Power Amplifier Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11248","display_name":"Advanced Power Amplifier Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12024","display_name":"Ultra-Wideband Communications Technology","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.761239767074585},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7276332974433899},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.5908750891685486},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.55263352394104},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.517080545425415},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4797728955745697},{"id":"https://openalex.org/keywords/sampling","display_name":"Sampling (signal processing)","score":0.428540974855423},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.42841672897338867},{"id":"https://openalex.org/keywords/adaptive-equalizer","display_name":"Adaptive equalizer","score":0.4157716929912567},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41211652755737305},{"id":"https://openalex.org/keywords/equalizer","display_name":"Equalizer","score":0.26146554946899414},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.2278459668159485},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.17080020904541016},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1214764416217804},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11272954940795898}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.761239767074585},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7276332974433899},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.5908750891685486},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.55263352394104},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.517080545425415},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4797728955745697},{"id":"https://openalex.org/C140779682","wikidata":"https://www.wikidata.org/wiki/Q210868","display_name":"Sampling (signal processing)","level":3,"score":0.428540974855423},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.42841672897338867},{"id":"https://openalex.org/C25125847","wikidata":"https://www.wikidata.org/wiki/Q4680741","display_name":"Adaptive equalizer","level":4,"score":0.4157716929912567},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41211652755737305},{"id":"https://openalex.org/C67545415","wikidata":"https://www.wikidata.org/wiki/Q5384218","display_name":"Equalizer","level":3,"score":0.26146554946899414},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.2278459668159485},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.17080020904541016},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1214764416217804},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11272954940795898},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/access.2024.3422802","is_oa":true,"landing_page_url":"http://dx.doi.org/10.1109/access.2024.3422802","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},{"id":"pmh:oai:art.torvergata.it:2108/440824","is_oa":false,"landing_page_url":"https://hdl.handle.net/2108/440824","pdf_url":null,"source":{"id":"https://openalex.org/S4306400993","display_name":"Cineca Institutional Research Information System (Tor Vergata University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I116067653","host_organization_name":"University of Rome Tor Vergata","host_organization_lineage":["https://openalex.org/I116067653"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:doaj.org/article:d12e704da9d14109a5c21878b9b76b97","is_oa":true,"landing_page_url":"https://doaj.org/article/d12e704da9d14109a5c21878b9b76b97","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Access, Vol 12, Pp 92560-92572 (2024)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1109/access.2024.3422802","is_oa":true,"landing_page_url":"http://dx.doi.org/10.1109/access.2024.3422802","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.7799999713897705,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W1487564550","https://openalex.org/W1518236483","https://openalex.org/W1535749512","https://openalex.org/W1971655433","https://openalex.org/W1993383501","https://openalex.org/W1999542175","https://openalex.org/W2018121187","https://openalex.org/W2018316963","https://openalex.org/W2028894938","https://openalex.org/W2029027380","https://openalex.org/W2034160227","https://openalex.org/W2056619098","https://openalex.org/W2091585203","https://openalex.org/W2102800590","https://openalex.org/W2120816439","https://openalex.org/W2129994276","https://openalex.org/W2138461490","https://openalex.org/W2147914016","https://openalex.org/W2156589135","https://openalex.org/W2157362358","https://openalex.org/W2594252507","https://openalex.org/W2798718343","https://openalex.org/W2810329387","https://openalex.org/W2896400814","https://openalex.org/W2918974607","https://openalex.org/W2944119945","https://openalex.org/W2968274685","https://openalex.org/W3106905816","https://openalex.org/W3149976863","https://openalex.org/W3213806748","https://openalex.org/W4315630863","https://openalex.org/W4390422140","https://openalex.org/W4391305544","https://openalex.org/W4396594836"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W2316202402","https://openalex.org/W2390348052","https://openalex.org/W2373535795","https://openalex.org/W1876592433","https://openalex.org/W2083269738"],"abstract_inverted_index":{"Hardware":[0],"implementations":[1],"represent":[2],"the":[3,19,22,41,49,70,73,93,101,112,127,138,144,163],"major":[4],"challenges":[5],"when":[6],"digital":[7,27,85],"signal":[8,119,176],"processors":[9],"for":[10,48,84],"ultra-wideband":[11],"(UWB)":[12],"signals":[13],"must":[14],"be":[15,38],"developed.":[16],"Due":[17],"to":[18,68,172],"limitation":[20,71],"of":[21,51,92,137,150],"maximum":[23,74],"clock":[24,75,129],"rate":[25],"in":[26,132,148],"devices,":[28],"systems":[29],"with":[30,120,143],"high":[31],"sampling":[32],"rates":[33],"(above":[34],"GHz)":[35],"cannot":[36],"easily":[37],"implemented.":[39],"In":[40,77],"literature,":[42],"several":[43,124],"works":[44],"propose":[45],"parallel":[46,82],"architectures":[47],"implementation":[50,165],"UWB.":[52],"They":[53],"are":[54,106],"implemented":[55],"on":[56,72,100,167],"Field-Programmable":[57],"Gate":[58],"Arrays":[59],"(FPGAs)":[60],"and":[61,66,88,157],"Application-Specific":[62],"Integrated":[63],"Circuits":[64],"(ASICs)":[65],"try":[67],"overcome":[69],"frequency.":[76],"this":[78],"work,":[79],"a":[80,117,121,168,174],"novel":[81],"architecture":[83],"UWB":[86,118,175],"equalizer":[87,114],"an":[89],"optimized":[90],"version":[91,136],"Least":[94],"Mean":[95],"Square":[96],"Block":[97,139,146],"(LMS)":[98],"based":[99,166],"Fast":[102,145],"FIR":[103],"Algorithms":[104],"(FFA)":[105],"presented.":[107],"Circuit":[108],"simulations":[109],"show":[110],"that":[111],"proposed":[113,135],"can":[115],"process":[116,173],"bandwidth":[122],"reaching":[123],"GHz,":[125],"using":[126],"typical":[128],"frequencies":[130],"available":[131],"FPGAs.":[133],"The":[134],"LMS":[140,147],"is":[141,181],"compared":[142],"terms":[149],"computational":[151],"complexity.":[152],"It":[153],"exhibits":[154],"better":[155],"results":[156],"greater":[158],"hardware":[159,164],"design":[160],"flexibility.":[161],"Finally,":[162],"Xilinx":[169],"Kintex":[170],"Ultrascale":[171],"sampled":[177],"at":[178],"1.6":[179],"GHz":[180],"described.":[182]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":14}],"updated_date":"2026-06-13T07:54:00.901334","created_date":"2025-10-10T00:00:00"}