{"id":"https://openalex.org/W4385696552","doi":"https://doi.org/10.1109/access.2023.3303840","title":"A Graph Neural Network Model for Fast and Accurate Quality of Result Estimation for High-Level Synthesis","display_name":"A Graph Neural Network Model for Fast and Accurate Quality of Result Estimation for High-Level Synthesis","publication_year":2023,"publication_date":"2023-01-01","ids":{"openalex":"https://openalex.org/W4385696552","doi":"https://doi.org/10.1109/access.2023.3303840"},"language":"en","primary_location":{"id":"doi:10.1109/access.2023.3303840","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2023.3303840","pdf_url":"https://ieeexplore.ieee.org/ielx7/6287639/6514899/10213402.pdf","source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://ieeexplore.ieee.org/ielx7/6287639/6514899/10213402.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065840983","display_name":"M. Usman Jamal","orcid":"https://orcid.org/0000-0002-1962-3764"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"M. Usman Jamal","raw_affiliation_strings":["Department of Electronics and Telecommunications, Politecnico di Torino, Turin, Italy","Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Turin, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060042692","display_name":"Zhuowei Li","orcid":"https://orcid.org/0000-0003-4631-3531"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Zhuowei Li","raw_affiliation_strings":["Department of Electronics and Telecommunications, Politecnico di Torino, Turin, Italy","Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Turin, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030646218","display_name":"Mihai T. Lazarescu","orcid":"https://orcid.org/0000-0003-0884-5158"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Mihai T. Lazarescu","raw_affiliation_strings":["Department of Electronics and Telecommunications, Politecnico di Torino, Turin, Italy","Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Turin, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050365912","display_name":"Luciano Lavagno","orcid":"https://orcid.org/0000-0002-9762-6522"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luciano Lavagno","raw_affiliation_strings":["Department of Electronics and Telecommunications, Politecnico di Torino, Turin, Italy","Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Turin, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5065840983"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":{"value":1850,"currency":"USD","value_usd":1850},"apc_paid":{"value":1850,"currency":"USD","value_usd":1850},"fwci":1.8027,"has_fulltext":true,"cited_by_count":6,"citation_normalized_percentile":{"value":0.84374048,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"11","issue":null,"first_page":"85785","last_page":"85798"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.8360140323638916},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8207821846008301},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6931279897689819},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5851349234580994},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.523706316947937},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4709625840187073},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4567502737045288},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.4499552845954895},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.44150322675704956},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43579578399658203},{"id":"https://openalex.org/keywords/data-flow-analysis","display_name":"Data-flow analysis","score":0.42498543858528137},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.38193297386169434},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.3230183720588684},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.18324467539787292},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1591690182685852}],"concepts":[{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.8360140323638916},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8207821846008301},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6931279897689819},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5851349234580994},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.523706316947937},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4709625840187073},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4567502737045288},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.4499552845954895},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.44150322675704956},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43579578399658203},{"id":"https://openalex.org/C88468194","wikidata":"https://www.wikidata.org/wiki/Q1172416","display_name":"Data-flow analysis","level":3,"score":0.42498543858528137},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.38193297386169434},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.3230183720588684},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.18324467539787292},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1591690182685852},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/access.2023.3303840","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2023.3303840","pdf_url":"https://ieeexplore.ieee.org/ielx7/6287639/6514899/10213402.pdf","source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:30a9de6576bd4e74bcb9dc37b98e8170","is_oa":true,"landing_page_url":"https://doaj.org/article/30a9de6576bd4e74bcb9dc37b98e8170","pdf_url":null,"source":{"id":"https://openalex.org/S112646816","display_name":"SHILAP Revista de lepidopterolog\u00eda","issn_l":"0300-5267","issn":["0300-5267","2340-4078"],"is_oa":true,"is_in_doaj":true,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Access, Vol 11, Pp 85785-85798 (2023)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1109/access.2023.3303840","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2023.3303840","pdf_url":"https://ieeexplore.ieee.org/ielx7/6287639/6514899/10213402.pdf","source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.49000000953674316,"id":"https://metadata.un.org/sdg/8","display_name":"Decent work and economic growth"}],"awards":[{"id":"https://openalex.org/G2020622295","display_name":null,"funder_award_id":"Big Data","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"},{"id":"https://openalex.org/G3514550006","display_name":null,"funder_award_id":"Centre","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"},{"id":"https://openalex.org/G3650733657","display_name":null,"funder_award_id":"NextGenerationEU","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"},{"id":"https://openalex.org/G5405180196","display_name":null,"funder_award_id":"101097224","funder_id":"https://openalex.org/F4320319005","funder_display_name":"Key Digital Technologies Joint Undertaking"},{"id":"https://openalex.org/G8024291379","display_name":"Reconfigurable Heterogeneous Highly Parallel Processing Platform for safe and secure AI","funder_award_id":"101097224","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"}],"funders":[{"id":"https://openalex.org/F4320310077","display_name":"National Research Centre","ror":"https://ror.org/02n85j827"},{"id":"https://openalex.org/F4320319005","display_name":"Key Digital Technologies Joint Undertaking","ror":null},{"id":"https://openalex.org/F4320320300","display_name":"European Commission","ror":"https://ror.org/00k4n6c32"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4385696552.pdf","grobid_xml":"https://content.openalex.org/works/W4385696552.grobid-xml"},"referenced_works_count":44,"referenced_works":["https://openalex.org/W1522301498","https://openalex.org/W2012114780","https://openalex.org/W2166029537","https://openalex.org/W2606780347","https://openalex.org/W2788211964","https://openalex.org/W2794046273","https://openalex.org/W2889669826","https://openalex.org/W2907492528","https://openalex.org/W2945759188","https://openalex.org/W2962711740","https://openalex.org/W2963285578","https://openalex.org/W2964015378","https://openalex.org/W2985324865","https://openalex.org/W2992137891","https://openalex.org/W3012450843","https://openalex.org/W3042770487","https://openalex.org/W3092027164","https://openalex.org/W3099375322","https://openalex.org/W3112616759","https://openalex.org/W3137672172","https://openalex.org/W3152893301","https://openalex.org/W3168189449","https://openalex.org/W3169517138","https://openalex.org/W3174263468","https://openalex.org/W3200354549","https://openalex.org/W4221158934","https://openalex.org/W4224265992","https://openalex.org/W4246166885","https://openalex.org/W4286795917","https://openalex.org/W4288419263","https://openalex.org/W4293023278","https://openalex.org/W4293025067","https://openalex.org/W4294558607","https://openalex.org/W4298385411","https://openalex.org/W6631190155","https://openalex.org/W6685562342","https://openalex.org/W6726873649","https://openalex.org/W6736685754","https://openalex.org/W6738964360","https://openalex.org/W6754929296","https://openalex.org/W6760045743","https://openalex.org/W6791113163","https://openalex.org/W6796783112","https://openalex.org/W6797464607"],"related_works":["https://openalex.org/W3011978806","https://openalex.org/W3204573923","https://openalex.org/W3207169898","https://openalex.org/W3198354237","https://openalex.org/W2743305891","https://openalex.org/W4385309418","https://openalex.org/W2331259470","https://openalex.org/W2142012722","https://openalex.org/W1903431847","https://openalex.org/W1528221867"],"abstract_inverted_index":{"High-level":[0],"synthesis":[1],"(HLS)":[2],"is":[3],"a":[4,138,143],"solution":[5],"for":[6,182],"rapid":[7],"prototyping":[8],"of":[9,43,65,69,77,107,137],"application-specific":[10],"hardware":[11,25],"using":[12],"the":[13,58,61,66,75,95,99,119,132,161,165,191],"C/C++":[14],"behavioral":[15],"programming":[16],"language.":[17],"Designers":[18],"can":[19,130],"apply":[20],"HLS":[21,36,109,121,167],"directives":[22],"to":[23,55,73,157,160,190],"optimize":[24],"implementations":[26],"by":[27,155,164,178],"making":[28,51],"trade-offs":[29,53],"between":[30],"cost":[31],"and":[32,93,134,175,177,180,185],"performance.":[33],"However,":[34],"current":[35],"tools":[37],"do":[38],"not":[39],"provide":[40],"reliable":[41],"quality":[42],"results":[44,125],"(QoR)":[45],"estimates,":[46],"which":[47],"prevents":[48],"designers":[49],"from":[50,98],"these":[52],"efficiently":[54],"ensure":[56],"that":[57,91,127],"design":[59,79,110,141],"meets":[60],"constraints.":[62],"Taking":[63],"advantage":[64],"widespread":[67],"use":[68],"machine":[70],"learning":[71],"(ML)":[72],"improve":[74],"predictability":[76],"electronic":[78],"automation":[80],"(EDA)":[81],"tools,":[82],"we":[83],"propose":[84],"several":[85],"graph":[86,104],"neural":[87],"network":[88],"(GNN)-based":[89],"models":[90],"learn":[92],"predict":[94],"post-implementation":[96],"QoR":[97],"pre-schedule":[100],"control":[101],"data":[102],"flow":[103],"(CDFG)":[105],"representation":[106],"an":[108],"targeting":[111],"field-programmable":[112],"gate":[113],"array":[114],"(FPGA)":[115],"implementation,":[116],"considering":[117],"also":[118],"user":[120],"optimization":[122],"directives.":[123],"Experimental":[124],"show":[126],"our":[128],"model":[129],"estimate":[131,162],"timing":[133,186],"resource":[135,183],"usage":[136,184],"previously":[139],"unseen":[140],"(i.e,":[142],"completely":[144],"new":[145],"CDFG)":[146],"within":[147],"milliseconds":[148],"with":[149],"high":[150],"accuracy,":[151],"reducing":[152],"prediction":[153],"errors":[154],"up":[156],"74%":[158],"compared":[159,189],"generated":[163],"Vitis":[166],"tool":[168],"itself":[169],"after":[170],"going":[171],"through":[172],"time-consuming":[173],"scheduling":[174],"binding,":[176],"29%":[179],"22%":[181],"prediction,":[187],"respectively,":[188],"state-of-the-art.":[192]},"counts_by_year":[{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":1}],"updated_date":"2026-04-18T07:56:08.524223","created_date":"2025-10-10T00:00:00"}