{"id":"https://openalex.org/W4294167332","doi":"https://doi.org/10.1109/access.2022.3203702","title":"Software-Level Memory Regulation to Reduce Execution Time Variation on Multicore Real-Time Systems","display_name":"Software-Level Memory Regulation to Reduce Execution Time Variation on Multicore Real-Time Systems","publication_year":2022,"publication_date":"2022-01-01","ids":{"openalex":"https://openalex.org/W4294167332","doi":"https://doi.org/10.1109/access.2022.3203702"},"language":"en","primary_location":{"id":"doi:10.1109/access.2022.3203702","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2022.3203702","pdf_url":"https://ieeexplore.ieee.org/ielx7/6287639/6514899/09874794.pdf","source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://ieeexplore.ieee.org/ielx7/6287639/6514899/09874794.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006627490","display_name":"Sihyeong Park","orcid":"https://orcid.org/0000-0001-8244-4817"},"institutions":[{"id":"https://openalex.org/I4210131650","display_name":"Korea Electronics Technology Institute","ror":"https://ror.org/039k6f508","country_code":"KR","type":"facility","lineage":["https://openalex.org/I2801339556","https://openalex.org/I4210089395","https://openalex.org/I4210131650"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sihyeong Park","raw_affiliation_strings":["SoC Platform Research Center, Korea Electronics Technology Institute, Seongnam-si, Republic of Korea","SoC Platform Research Center, Korea Electronics Technology Institute, Seongnam-si, Gyeonggi-do, Republic of Korea"],"raw_orcid":"https://orcid.org/0000-0001-8244-4817","affiliations":[{"raw_affiliation_string":"SoC Platform Research Center, Korea Electronics Technology Institute, Seongnam-si, Republic of Korea","institution_ids":["https://openalex.org/I4210131650"]},{"raw_affiliation_string":"SoC Platform Research Center, Korea Electronics Technology Institute, Seongnam-si, Gyeonggi-do, Republic of Korea","institution_ids":["https://openalex.org/I4210131650"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101558196","display_name":"Jemin Lee","orcid":"https://orcid.org/0000-0002-9332-3508"},"institutions":[{"id":"https://openalex.org/I142401562","display_name":"Electronics and Telecommunications Research Institute","ror":"https://ror.org/03ysstz10","country_code":"KR","type":"facility","lineage":["https://openalex.org/I142401562","https://openalex.org/I2801339556","https://openalex.org/I4210144908","https://openalex.org/I4387152098"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jemin Lee","raw_affiliation_strings":["Artificial Intelligence Research Laboratory, Electronics and Telecommunications Research Institute, Daejeon, Republic of Korea"],"raw_orcid":"https://orcid.org/0000-0002-9332-3508","affiliations":[{"raw_affiliation_string":"Artificial Intelligence Research Laboratory, Electronics and Telecommunications Research Institute, Daejeon, Republic of Korea","institution_ids":["https://openalex.org/I142401562"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037418978","display_name":"Hyungshin Kim","orcid":"https://orcid.org/0000-0001-9615-1644"},"institutions":[{"id":"https://openalex.org/I196345858","display_name":"Chungnam National University","ror":"https://ror.org/0227as991","country_code":"KR","type":"education","lineage":["https://openalex.org/I196345858"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Hyungshin Kim","raw_affiliation_strings":["The Division of Computer Convergence, Chungnam National University, Daejeon, Republic of Korea"],"raw_orcid":"https://orcid.org/0000-0001-9615-1644","affiliations":[{"raw_affiliation_string":"The Division of Computer Convergence, Chungnam National University, Daejeon, Republic of Korea","institution_ids":["https://openalex.org/I196345858"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":1850,"currency":"USD","value_usd":1850},"apc_paid":{"value":1850,"currency":"USD","value_usd":1850},"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.10179211,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"10","issue":null,"first_page":"93799","last_page":"93811"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9933000206947327,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9923999905586243,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8998295068740845},{"id":"https://openalex.org/keywords/worst-case-execution-time","display_name":"Worst-case execution time","score":0.6182032227516174},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5622220039367676},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5464129447937012},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.537036657333374},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.47873637080192566},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.45150718092918396},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.43623995780944824},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.43323832750320435},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.4116983711719513},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.41164132952690125},{"id":"https://openalex.org/keywords/execution-time","display_name":"Execution time","score":0.3947504162788391},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3875368535518646},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3574880361557007},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.2802817225456238},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.19285225868225098},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.13066405057907104}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8998295068740845},{"id":"https://openalex.org/C200130814","wikidata":"https://www.wikidata.org/wiki/Q362858","display_name":"Worst-case execution time","level":3,"score":0.6182032227516174},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5622220039367676},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5464129447937012},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.537036657333374},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.47873637080192566},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.45150718092918396},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.43623995780944824},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.43323832750320435},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.4116983711719513},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.41164132952690125},{"id":"https://openalex.org/C2989134064","wikidata":"https://www.wikidata.org/wiki/Q288510","display_name":"Execution time","level":2,"score":0.3947504162788391},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3875368535518646},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3574880361557007},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.2802817225456238},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.19285225868225098},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.13066405057907104},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/access.2022.3203702","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2022.3203702","pdf_url":"https://ieeexplore.ieee.org/ielx7/6287639/6514899/09874794.pdf","source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:ca921b94d42d4b9581c9783b23c8974c","is_oa":true,"landing_page_url":"https://doaj.org/article/ca921b94d42d4b9581c9783b23c8974c","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Access, Vol 10, Pp 93799-93811 (2022)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1109/access.2022.3203702","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2022.3203702","pdf_url":"https://ieeexplore.ieee.org/ielx7/6287639/6514899/09874794.pdf","source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4294167332.pdf","grobid_xml":"https://content.openalex.org/works/W4294167332.grobid-xml"},"referenced_works_count":26,"referenced_works":["https://openalex.org/W1604530876","https://openalex.org/W1993079513","https://openalex.org/W2005296098","https://openalex.org/W2061663604","https://openalex.org/W2100122997","https://openalex.org/W2122969894","https://openalex.org/W2155815531","https://openalex.org/W2267268515","https://openalex.org/W2557271002","https://openalex.org/W2790507270","https://openalex.org/W2890473121","https://openalex.org/W2915541671","https://openalex.org/W2944954218","https://openalex.org/W2996532023","https://openalex.org/W2999066514","https://openalex.org/W2999781197","https://openalex.org/W3016568802","https://openalex.org/W3032064336","https://openalex.org/W3131395107","https://openalex.org/W3160220816","https://openalex.org/W3166673447","https://openalex.org/W4224216473","https://openalex.org/W4226365305","https://openalex.org/W4232751114","https://openalex.org/W4253679649","https://openalex.org/W6760942226"],"related_works":["https://openalex.org/W2105141138","https://openalex.org/W2781952239","https://openalex.org/W1848192231","https://openalex.org/W254684032","https://openalex.org/W1495085183","https://openalex.org/W4230333905","https://openalex.org/W3151393245","https://openalex.org/W1942416056","https://openalex.org/W2247651031","https://openalex.org/W2339366892"],"abstract_inverted_index":{"Modern":[0],"real-time":[1,37],"embedded":[2],"systems":[3],"are":[4],"equipped":[5],"with":[6],"multi-core":[7,15],"processors":[8],"to":[9,43,70,81,89,188],"execute":[10],"computationally":[11],"intensive":[12],"tasks.":[13,38],"In":[14],"architecture,":[16],"last-level":[17],"cache":[18,26],"memory":[19,62,68,105,112,120,175],"is":[20,122,131],"shared":[21,25,55],"by":[22,186],"cores.":[23],"The":[24,142],"becomes":[27],"a":[28,41,45,54,126],"non-deterministic":[29],"resource,":[30],"which":[31],"affects":[32],"the":[33,84,100,108,116,139,150,153,171,181],"independent":[34],"execution":[35,48,73,86,158,184],"of":[36,111,135,152],"We":[39],"propose":[40],"solution":[42],"remedy":[44],"variation":[46,182],"in":[47,53,92,133,183],"time":[49,87,185],"when":[50,190],"interference":[51,191],"happens":[52],"cache.":[56],"Current":[57],"solutions":[58],"have":[59],"relied":[60],"on":[61,125],"scheduling":[63],"approaches":[64],"that":[65,130,170],"avoid":[66],"concurrent":[67],"access":[69,106],"guarantee":[71],"deterministic":[72],"time.":[74,166],"However,":[75],"these":[76],"methods":[77],"required":[78],"complex":[79],"analysis":[80,129,165],"accurately":[82],"estimate":[83],"worst-case":[85],"and":[88],"schedule":[90],"tasks":[91],"an":[93],"overly":[94],"conservative":[95],"manner.":[96],"Unlike":[97],"existing":[98],"works,":[99],"proposed":[101,143,172],"method":[102,144,178],"prevents":[103],"simultaneous":[104],"using":[107,138],"side":[109],"effect":[110],"barriers":[113],"rather":[114],"than":[115],"complicated":[117],"analysis.":[118],"A":[119],"barrier":[121,176],"inserted":[123],"based":[124],"simple":[127],"code":[128],"performed":[132],"units":[134],"basic":[136,173],"blocks":[137],"LLVM":[140],"compiler.":[141],"not":[145,148],"only":[146],"does":[147],"require":[149],"modification":[151],"operating":[154],"system":[155],"or":[156],"task":[157],"flow":[159],"but":[160],"also":[161],"relatively":[162],"shows":[163],"fast":[164],"Experimental":[167],"results":[168],"show":[169],"block-based":[174],"insertion":[177],"can":[179],"reduce":[180],"up":[187],"80%":[189],"occurs.":[192]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}