{"id":"https://openalex.org/W3206405179","doi":"https://doi.org/10.1109/access.2021.3119633","title":"Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs","display_name":"Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs","publication_year":2021,"publication_date":"2021-01-01","ids":{"openalex":"https://openalex.org/W3206405179","doi":"https://doi.org/10.1109/access.2021.3119633","mag":"3206405179"},"language":"en","primary_location":{"id":"doi:10.1109/access.2021.3119633","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2021.3119633","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1109/access.2021.3119633","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025171789","display_name":"Luis Alberto Aranda","orcid":"https://orcid.org/0000-0003-4458-9761"},"institutions":[{"id":"https://openalex.org/I3020445194","display_name":"Universidad Nebrija","ror":"https://ror.org/03tzyrt94","country_code":"ES","type":"education","lineage":["https://openalex.org/I3020445194"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Luis Alberto Aranda","raw_affiliation_strings":["ARIES Research Center, Universidad Antonio de Nebrija, Madrid 28040, Spain. (e-mail: luis.aranda89@gmail.com)","ARIES research center, Universidad Antonio de Nebrija, Madrid, Spain"],"raw_orcid":"https://orcid.org/0000-0003-4458-9761","affiliations":[{"raw_affiliation_string":"ARIES Research Center, Universidad Antonio de Nebrija, Madrid 28040, Spain. (e-mail: luis.aranda89@gmail.com)","institution_ids":["https://openalex.org/I3020445194"]},{"raw_affiliation_string":"ARIES research center, Universidad Antonio de Nebrija, Madrid, Spain","institution_ids":["https://openalex.org/I3020445194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074611037","display_name":"O. Ruano","orcid":"https://orcid.org/0000-0001-8275-1745"},"institutions":[{"id":"https://openalex.org/I3020445194","display_name":"Universidad Nebrija","ror":"https://ror.org/03tzyrt94","country_code":"ES","type":"education","lineage":["https://openalex.org/I3020445194"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Oscar Ruano","raw_affiliation_strings":["ARIES Research Center, Universidad Antonio de Nebrija, Madrid 28040, Spain"],"raw_orcid":"https://orcid.org/0000-0001-8275-1745","affiliations":[{"raw_affiliation_string":"ARIES Research Center, Universidad Antonio de Nebrija, Madrid 28040, Spain","institution_ids":["https://openalex.org/I3020445194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088891897","display_name":"Francisco Garc\u00eda-Herrero","orcid":"https://orcid.org/0000-0001-6719-9681"},"institutions":[{"id":"https://openalex.org/I3020445194","display_name":"Universidad Nebrija","ror":"https://ror.org/03tzyrt94","country_code":"ES","type":"education","lineage":["https://openalex.org/I3020445194"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Francisco Garcia-Herrero","raw_affiliation_strings":["ARIES Research Center, Universidad Antonio de Nebrija, Madrid 28040, Spain"],"raw_orcid":"https://orcid.org/0000-0001-6719-9681","affiliations":[{"raw_affiliation_string":"ARIES Research Center, Universidad Antonio de Nebrija, Madrid 28040, Spain","institution_ids":["https://openalex.org/I3020445194"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044495372","display_name":"Juan Antonio Maestro","orcid":"https://orcid.org/0000-0001-7133-9026"},"institutions":[{"id":"https://openalex.org/I121748325","display_name":"Universidad Complutense de Madrid","ror":"https://ror.org/02p0gd045","country_code":"ES","type":"education","lineage":["https://openalex.org/I121748325"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Juan Antonio Maestro","raw_affiliation_strings":["Department of Computer Architecture and Automatics, Computer Science Faculty, Complutense University of Madrid, Madrid 28040, Spain"],"raw_orcid":"https://orcid.org/0000-0001-7133-9026","affiliations":[{"raw_affiliation_string":"Department of Computer Architecture and Automatics, Computer Science Faculty, Complutense University of Madrid, Madrid 28040, Spain","institution_ids":["https://openalex.org/I121748325"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":1850,"currency":"USD","value_usd":1850},"apc_paid":{"value":1850,"currency":"USD","value_usd":1850},"fwci":0.295,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.55973968,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"9","issue":null,"first_page":"140676","last_page":"140685"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8287950158119202},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7665362358093262},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6202200651168823},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.5529400110244751},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5488345623016357},{"id":"https://openalex.org/keywords/unavailability","display_name":"Unavailability","score":0.5327040553092957},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5268030166625977},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.48257890343666077},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.46314263343811035},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3293430805206299},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14419707655906677},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.10670474171638489}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8287950158119202},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7665362358093262},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6202200651168823},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.5529400110244751},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5488345623016357},{"id":"https://openalex.org/C2780505938","wikidata":"https://www.wikidata.org/wiki/Q17093282","display_name":"Unavailability","level":2,"score":0.5327040553092957},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5268030166625977},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.48257890343666077},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.46314263343811035},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3293430805206299},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14419707655906677},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.10670474171638489},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/access.2021.3119633","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2021.3119633","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:8efc69b1b6f84aad9e9fbe8a21e1d94a","is_oa":true,"landing_page_url":"https://doaj.org/article/8efc69b1b6f84aad9e9fbe8a21e1d94a","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Access, Vol 9, Pp 140676-140685 (2021)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1109/access.2021.3119633","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2021.3119633","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4000000059604645}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1590251127","https://openalex.org/W1598941862","https://openalex.org/W1950970151","https://openalex.org/W1976834654","https://openalex.org/W2015748182","https://openalex.org/W2017284812","https://openalex.org/W2098513789","https://openalex.org/W2113191061","https://openalex.org/W2115071828","https://openalex.org/W2135254996","https://openalex.org/W2135577965","https://openalex.org/W2144537998","https://openalex.org/W2152652532","https://openalex.org/W2533291033","https://openalex.org/W2678723747","https://openalex.org/W2769840268","https://openalex.org/W2781738013","https://openalex.org/W2906572788","https://openalex.org/W2966322427","https://openalex.org/W2971478958","https://openalex.org/W3100931082","https://openalex.org/W3133015476"],"related_works":["https://openalex.org/W4237235066","https://openalex.org/W207884067","https://openalex.org/W3127016596","https://openalex.org/W2026539069","https://openalex.org/W2365973415","https://openalex.org/W3146085540","https://openalex.org/W1482423459","https://openalex.org/W1485756991","https://openalex.org/W2376218453","https://openalex.org/W2984236338"],"abstract_inverted_index":{"There":[0],"are":[1,24],"many":[2],"platforms":[3],"and":[4,60,130,180,184],"tools":[5],"based":[6],"on":[7,28],"field-programmable":[8],"gate":[9],"array":[10],"(FPGA)":[11],"devices":[12,75],"oriented":[13],"to":[14,54,66,91,95,98,120,146],"facilitate":[15],"the":[16,33,37,40,56,83,112,121,128,131,168],"reliability":[17,187],"estimation":[18],"of":[19,39,58,85,89,106,115,123,127,133,167],"digital":[20],"designs,":[21],"but":[22],"they":[23],"usually":[25],"focused":[26],"only":[27],"configuration":[29,34,149],"memory":[30,35,41,150],"errors":[31,62],"since":[32],"represents":[36],"majority":[38],"elements":[42],"in":[43,68,110,163,176,186],"an":[44,47],"FPGA.":[45],"However,":[46],"FPGA-based":[48],"platform":[49],"could":[50],"also":[51],"be":[52,96],"exploited":[53],"support":[55],"emulation":[57],"transient":[59,161],"permanent":[61,159],"for":[63,189],"designs":[64],"intended":[65],"work":[67],"application-specific":[69],"integrated":[70],"circuits":[71],"(ASICs)":[72],"or":[73,160],"radiation-hardened":[74],"such":[76],"as":[77],"antifuse":[78],"FPGAs.":[79],"In":[80],"this":[81,107,140],"context,":[82],"obtention":[84],"a":[86,124,144],"particular":[87],"set":[88,114],"bits":[90,151],"flip":[92],"is":[93,118,174],"required":[94],"able":[97],"emulate":[99,158],"these":[100],"error":[101],"models.":[102],"The":[103],"main":[104],"difficulty":[105],"approach":[108],"lies":[109],"determining":[111],"mentioned":[113],"bits,":[116],"which":[117],"due":[119],"unavailability":[122],"public":[125],"description":[126],"bitstream":[129],"lack":[132],"FPGA":[134,178],"architecture":[135],"details.":[136],"To":[137],"help":[138],"with":[139],"issue,":[141],"we":[142],"present":[143],"methodology":[145,173],"determine":[147],"specific":[148],"from":[152],"SRAM-based":[153],"FPGAs":[154],"that,":[155],"when":[156],"flipped,":[157],"upsets":[162],"any":[164],"flip-flop":[165],"element":[166],"design":[169],"under":[170],"test.":[171],"This":[172],"proved":[175],"recent":[177],"technologies":[179],"provides":[181],"great":[182],"control":[183],"precision":[185],"experiments":[188],"harsh":[190],"environments.":[191]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}