{"id":"https://openalex.org/W3138331464","doi":"https://doi.org/10.1109/access.2021.3067453","title":"High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs","display_name":"High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs","publication_year":2021,"publication_date":"2021-01-01","ids":{"openalex":"https://openalex.org/W3138331464","doi":"https://doi.org/10.1109/access.2021.3067453","mag":"3138331464"},"language":"en","primary_location":{"id":"doi:10.1109/access.2021.3067453","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2021.3067453","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1109/access.2021.3067453","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043923553","display_name":"Osama Bin Tariq","orcid":"https://orcid.org/0000-0001-5398-4072"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Osama Bin Tariq","raw_affiliation_strings":["Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059220833","display_name":"Junnan Shan","orcid":"https://orcid.org/0000-0001-9405-8825"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Junnan Shan","raw_affiliation_strings":["Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066445455","display_name":"George Floros","orcid":"https://orcid.org/0000-0002-2867-9604"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Georgios Floros","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Thessaly, Volos, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103066371","display_name":"Christos Sotiriou","orcid":"https://orcid.org/0000-0001-9318-474X"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Christos P. Sotiriou","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Thessaly, Volos, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036528695","display_name":"Mario R. Casu","orcid":"https://orcid.org/0000-0002-1026-0178"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Mario R. Casu","raw_affiliation_strings":["Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030646218","display_name":"Mihai T. Lazarescu","orcid":"https://orcid.org/0000-0003-0884-5158"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Mihai Teodor Lazarescu","raw_affiliation_strings":["Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050365912","display_name":"Luciano Lavagno","orcid":"https://orcid.org/0000-0002-9762-6522"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luciano Lavagno","raw_affiliation_strings":["Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5043923553"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":{"value":1850,"currency":"USD","value_usd":1850},"apc_paid":{"value":1850,"currency":"USD","value_usd":1850},"fwci":2.3462,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.88130106,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"9","issue":null,"first_page":"54286","last_page":"54297"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8477524518966675},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6930545568466187},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5974979996681213},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5408499836921692},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5184197425842285},{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.48902377486228943},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.487050324678421},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4774742126464844},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.41798681020736694},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35734039545059204},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3348326086997986},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18985134363174438}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8477524518966675},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6930545568466187},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5974979996681213},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5408499836921692},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5184197425842285},{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.48902377486228943},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.487050324678421},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4774742126464844},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.41798681020736694},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35734039545059204},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3348326086997986},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18985134363174438},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/access.2021.3067453","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2021.3067453","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:db168a37c1c041648add24fffb055994","is_oa":true,"landing_page_url":"https://doaj.org/article/db168a37c1c041648add24fffb055994","pdf_url":null,"source":{"id":"https://openalex.org/S112646816","display_name":"SHILAP Revista de lepidopterolog\u00eda","issn_l":"0300-5267","issn":["0300-5267","2340-4078"],"is_oa":true,"is_in_doaj":true,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Access, Vol 9, Pp 54286-54297 (2021)","raw_type":"article"},{"id":"pmh:oai:ir.lib.uth.gr:11615/79614","is_oa":false,"landing_page_url":"http://hdl.handle.net/11615/79614","pdf_url":null,"source":{"id":"https://openalex.org/S4306400243","display_name":"University of Thessaly Institutional Repository (University of Thessaly)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I145722265","host_organization_name":"University of Thessaly","host_organization_lineage":["https://openalex.org/I145722265"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Access","raw_type":"journalArticle"},{"id":"pmh:oai:zenodo.org:102593","is_oa":true,"landing_page_url":"https://www.openaccessrepository.it/record/102593","pdf_url":null,"source":{"id":"https://openalex.org/S4306402478","display_name":"INFM-OAR (INFN Catania)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210116497","host_organization_name":"Istituto Nazionale di Fisica Nucleare, Sezione di Catania","host_organization_lineage":["https://openalex.org/I4210116497"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"doi:10.1109/access.2021.3067453","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2021.3067453","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.9100000262260437}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":42,"referenced_works":["https://openalex.org/W1980040075","https://openalex.org/W2006026409","https://openalex.org/W2033863865","https://openalex.org/W2047631674","https://openalex.org/W2073137766","https://openalex.org/W2074799901","https://openalex.org/W2090971357","https://openalex.org/W2107980957","https://openalex.org/W2113753459","https://openalex.org/W2145308009","https://openalex.org/W2146051689","https://openalex.org/W2153185479","https://openalex.org/W2156666436","https://openalex.org/W2328615082","https://openalex.org/W2343695530","https://openalex.org/W2533722497","https://openalex.org/W2542189141","https://openalex.org/W2593789631","https://openalex.org/W2738078952","https://openalex.org/W2771551340","https://openalex.org/W2788211964","https://openalex.org/W2799882197","https://openalex.org/W2810307706","https://openalex.org/W2886700560","https://openalex.org/W2897505503","https://openalex.org/W2903881552","https://openalex.org/W2914252251","https://openalex.org/W2918462279","https://openalex.org/W2939908742","https://openalex.org/W2944730674","https://openalex.org/W2962193180","https://openalex.org/W2983726556","https://openalex.org/W3007959289","https://openalex.org/W3041521987","https://openalex.org/W3092394454","https://openalex.org/W3131482099","https://openalex.org/W4232880828","https://openalex.org/W4239385313","https://openalex.org/W4246166885","https://openalex.org/W4378832451","https://openalex.org/W6658865270","https://openalex.org/W6774187331"],"related_works":["https://openalex.org/W4319430423","https://openalex.org/W4390224957","https://openalex.org/W2993910401","https://openalex.org/W4323831234","https://openalex.org/W2544043553","https://openalex.org/W2121309702","https://openalex.org/W1982685694","https://openalex.org/W49599899","https://openalex.org/W4311839959","https://openalex.org/W3217774925"],"abstract_inverted_index":{"Ever":[0],"since":[1],"transistor":[2],"cost":[3],"stopped":[4],"decreasing,":[5],"customized":[6],"programmable":[7],"platforms,":[8],"such":[9,53],"as":[10,54],"field-programmable":[11],"gate":[12],"arrays":[13],"(FPGAs),":[14],"became":[15],"a":[16,106],"major":[17],"way":[18],"to":[19,35,78,192,202],"improve":[20],"software":[21,28],"execution":[22],"performance":[23],"and":[24,50,88,95,130,150,201],"energy":[25],"consumption.":[26],"While":[27],"developers":[29],"can":[30,56],"use":[31],"high-level":[32,107],"synthesis":[33],"(HLS)":[34],"speed":[36],"up":[37],"register-transfer":[38],"level":[39,119,200],"(RTL)":[40],"code":[41,149],"generation":[42],"from":[43,73,124],"C++":[44],"or":[45,64,160],"OpenCL":[46],"source":[47,102,118,148,199],"code,":[48],"placement":[49],"routing":[51,113,174],"issues,":[52],"congestion,":[55],"still":[57],"prevent":[58],"achieving":[59],"an":[60],"FPGA":[61,68,126],"programming":[62],"bitstream":[63],"dramatically":[65],"reduce":[66],"the":[67,92,98,101,112,117,122,125,131,136,147,153,157,161,167,185,198],"implementation":[69],"performance.":[70],"Congestion":[71],"reports":[72,123],"physical":[74,127],"design":[75,128],"tools":[76,129],"refer":[77],"thousands":[79],"of":[80,85,97,135],"RTL":[81],"signal":[82],"names":[83],"instead":[84],"developer-accessible":[86],"identifiers":[87],"statements,":[89],"considerably":[90],"complicating":[91],"developer":[93],"understanding":[94],"resolution":[96],"issues":[99,115],"at":[100,116,197],"level.":[103],"We":[104,178],"propose":[105],"back-annotation":[108],"flow":[109,140,190],"that":[110],"summarizes":[111],"congestion":[114,142,154,195],"by":[120,188],"analyzing":[121],"internal":[132],"debugging":[133],"files":[134],"HLS":[137,207],"tools.":[138],"Our":[139],"describes":[141],"using":[143,205],"comments":[144],"back-annotated":[145],"on":[146,176,180],"identifies":[151],"if":[152],"causes":[155,196],"are":[156,166],"on-chip":[158],"memories":[159],"DSP":[162],"units":[163],"(multipliers/adders),":[164],"which":[165],"shared":[168],"resources":[169],"very":[170],"often":[171],"associated":[172],"with":[173],"problems":[175],"FPGAs.":[177],"demonstrate":[179],"realistic":[181],"large":[182],"designs":[183],"how":[184],"information":[186],"provided":[187],"our":[189],"helps":[191],"quickly":[193],"spot":[194],"solve":[203],"them":[204],"appropriate":[206],"directives.":[208]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":6},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}