{"id":"https://openalex.org/W3113313543","doi":"https://doi.org/10.1109/access.2020.3043243","title":"A Quadrature PLL With Phase Mismatch Calibration for 32GS/s Time-Interleaved ADC","display_name":"A Quadrature PLL With Phase Mismatch Calibration for 32GS/s Time-Interleaved ADC","publication_year":2020,"publication_date":"2020-01-01","ids":{"openalex":"https://openalex.org/W3113313543","doi":"https://doi.org/10.1109/access.2020.3043243","mag":"3113313543"},"language":"en","primary_location":{"id":"doi:10.1109/access.2020.3043243","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2020.3043243","pdf_url":"https://ieeexplore.ieee.org/ielx7/6287639/6514899/09286446.pdf","source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://ieeexplore.ieee.org/ielx7/6287639/6514899/09286446.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063433812","display_name":"Shunli Ma","orcid":"https://orcid.org/0000-0002-2737-9845"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shunli Ma","raw_affiliation_strings":["State-Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0002-2737-9845","affiliations":[{"raw_affiliation_string":"State-Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001335523","display_name":"Tianxiang Wu","orcid":"https://orcid.org/0000-0003-4920-9932"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Tianxiang Wu","raw_affiliation_strings":["State-Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State-Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5016448886","display_name":"Junyan Ren","orcid":"https://orcid.org/0000-0002-7799-6251"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Junyan Ren","raw_affiliation_strings":["State-Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0002-7799-6251","affiliations":[{"raw_affiliation_string":"State-Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":{"value":1850,"currency":"USD","value_usd":1850},"apc_paid":{"value":1850,"currency":"USD","value_usd":1850},"fwci":0.0,"has_fulltext":true,"cited_by_count":1,"citation_normalized_percentile":{"value":0.13505395,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"8","issue":null,"first_page":"219695","last_page":"219708"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.801132082939148},{"id":"https://openalex.org/keywords/dbc","display_name":"dBc","score":0.6605490446090698},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.6242613196372986},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5677582621574402},{"id":"https://openalex.org/keywords/quadrature","display_name":"Quadrature (astronomy)","score":0.5467991232872009},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4509229362010956},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4441404640674591},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20645996928215027}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.801132082939148},{"id":"https://openalex.org/C193523891","wikidata":"https://www.wikidata.org/wiki/Q1771950","display_name":"dBc","level":3,"score":0.6605490446090698},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.6242613196372986},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5677582621574402},{"id":"https://openalex.org/C62869609","wikidata":"https://www.wikidata.org/wiki/Q28137","display_name":"Quadrature (astronomy)","level":2,"score":0.5467991232872009},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4509229362010956},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4441404640674591},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20645996928215027}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/access.2020.3043243","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2020.3043243","pdf_url":"https://ieeexplore.ieee.org/ielx7/6287639/6514899/09286446.pdf","source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:065771c7c2684e9790895ddd40e88a61","is_oa":true,"landing_page_url":"https://doaj.org/article/065771c7c2684e9790895ddd40e88a61","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Access, Vol 8, Pp 219695-219708 (2020)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1109/access.2020.3043243","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2020.3043243","pdf_url":"https://ieeexplore.ieee.org/ielx7/6287639/6514899/09286446.pdf","source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8999999761581421}],"awards":[{"id":"https://openalex.org/G5636211430","display_name":null,"funder_award_id":"2018YFB2202500","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G6622091460","display_name":null,"funder_award_id":"61934008","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G7423090522","display_name":null,"funder_award_id":"JIH1233034","funder_id":"https://openalex.org/F4320321851","funder_display_name":"Fudan University"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320321851","display_name":"Fudan University","ror":"https://ror.org/013q1eq08"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W3113313543.pdf","grobid_xml":"https://content.openalex.org/works/W3113313543.grobid-xml"},"referenced_works_count":31,"referenced_works":["https://openalex.org/W2016167819","https://openalex.org/W2038874999","https://openalex.org/W2043148724","https://openalex.org/W2044506147","https://openalex.org/W2064032656","https://openalex.org/W2075937341","https://openalex.org/W2099671724","https://openalex.org/W2103745509","https://openalex.org/W2104611393","https://openalex.org/W2104728238","https://openalex.org/W2105317509","https://openalex.org/W2106432827","https://openalex.org/W2106687953","https://openalex.org/W2128889905","https://openalex.org/W2137219772","https://openalex.org/W2152597771","https://openalex.org/W2154473497","https://openalex.org/W2158017712","https://openalex.org/W2161770961","https://openalex.org/W2169047810","https://openalex.org/W2313921896","https://openalex.org/W2328798527","https://openalex.org/W2580715839","https://openalex.org/W2631197814","https://openalex.org/W2802595552","https://openalex.org/W2810113582","https://openalex.org/W2889420974","https://openalex.org/W2893200225","https://openalex.org/W2906404755","https://openalex.org/W2926344714","https://openalex.org/W2947208032"],"related_works":["https://openalex.org/W2540832666","https://openalex.org/W4286579627","https://openalex.org/W1851259350","https://openalex.org/W272184114","https://openalex.org/W2117747481","https://openalex.org/W2394282069","https://openalex.org/W3189810088","https://openalex.org/W2141726610","https://openalex.org/W4281672152","https://openalex.org/W2474043983"],"abstract_inverted_index":{"This":[0],"article":[1],"presents":[2],"an":[3],"accurate":[4,93],"quadrature":[5,10,36,51,67,94,110],"phase-locked":[6],"loop":[7],"(PLL)":[8],"with":[9,53,109,128,141],"phase":[11,37,54,79,95,157,182],"mismatch":[12],"calibration":[13,55,184],"for":[14,78,96,112],"32":[15,113],"GS/s":[16,114],"analog-to-digital":[17],"converter":[18],"(ADC).":[19],"Due":[20],"to":[21,71,124],"the":[22,32,35,39,47,66,73,83,88,156,160,169,178,181],"mismatches":[23],"of":[24,31,38,65,104,159,180],"clock":[25,41,119,161],"distribution":[26],"in":[27,58,137],"layout":[28],"and":[29,75,85],"variations":[30],"active":[33],"devices,":[34],"sampling":[40,99,115,170],"is":[42,56,69,106,162,172,185],"significantly":[43],"deteriorated.":[44],"To":[45],"solve":[46],"problem,":[48],"a":[49,62],"novel":[50],"divider":[52,68],"induced":[57],"PLL":[59,90,105,134],"loop.":[60],"Moreover,":[61],"theoretical":[63,84],"model":[64,86],"proposed":[70,89,118,133,176],"predict":[72],"performance":[74],"potential":[76],"ability":[77],"calibration.":[80],"Based":[81],"on":[82],"analysis,":[87],"can":[91,120],"realize":[92,121],"high-speed":[97],"real-time":[98],"system.":[100],"The":[101,117,132],"output":[102],"frequency":[103,167],"8":[107],"GHz":[108,130],"phases":[111],"rate.":[116],"8-bit":[122],"signal":[123],"noise":[125,158],"ratio":[126],"requirement":[127],"16":[129],"bandwidth.":[131],"was":[135],"fabricated":[136],"65-nm":[138],"CMOS":[139],"process":[140],"28":[142],"mW":[143],"dc":[144],"power":[145],"consumption":[146],"under":[147],"1.2":[148],"V":[149],"supply":[150],"voltage.":[151],"Testing":[152],"results":[153],"show":[154],"that":[155],"-127":[163],"dBc/Hz":[164],"@10":[165],"MHz-offset":[166],"when":[168],"speed":[171],"27.4":[173],"GS/s.":[174],"With":[175],"methods,":[177],"range":[179],"error":[183],"around":[186],"\u00b120\u00b0.":[187]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}