{"id":"https://openalex.org/W2965136699","doi":"https://doi.org/10.1109/access.2019.2932647","title":"FPGA as a Hardware Accelerator for Computation Intensive Maximum Likelihood Expectation Maximization Medical Image Reconstruction Algorithm","display_name":"FPGA as a Hardware Accelerator for Computation Intensive Maximum Likelihood Expectation Maximization Medical Image Reconstruction Algorithm","publication_year":2019,"publication_date":"2019-01-01","ids":{"openalex":"https://openalex.org/W2965136699","doi":"https://doi.org/10.1109/access.2019.2932647","mag":"2965136699"},"language":"en","primary_location":{"id":"doi:10.1109/access.2019.2932647","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2019.2932647","pdf_url":"https://ieeexplore.ieee.org/ielx7/6287639/8600701/08784190.pdf","source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://ieeexplore.ieee.org/ielx7/6287639/8600701/08784190.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041882769","display_name":"Murali Ravi","orcid":"https://orcid.org/0000-0003-3459-6749"},"institutions":[{"id":"https://openalex.org/I4819740","display_name":"Sri Sathya Sai Institute of Higher Learning","ror":"https://ror.org/05arzt710","country_code":"IN","type":"education","lineage":["https://openalex.org/I4819740"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Murali Ravi","raw_affiliation_strings":["Sri Sathya Sai Institute of Higher Learning, Anantapur, India"],"raw_orcid":"https://orcid.org/0000-0003-3459-6749","affiliations":[{"raw_affiliation_string":"Sri Sathya Sai Institute of Higher Learning, Anantapur, India","institution_ids":["https://openalex.org/I4819740"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037673760","display_name":"Angu Sewa","orcid":"https://orcid.org/0000-0002-4179-5714"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Angu Sewa","raw_affiliation_strings":["Analog Devices Inc., Bengaluru, India"],"raw_orcid":"https://orcid.org/0000-0002-4179-5714","affiliations":[{"raw_affiliation_string":"Analog Devices Inc., Bengaluru, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020165409","display_name":"Shashidhar T.G.","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Shashidhar T.G.","raw_affiliation_strings":["Qualcomm, Bengaluru, India"],"raw_orcid":"https://orcid.org/0000-0003-1311-8780","affiliations":[{"raw_affiliation_string":"Qualcomm, Bengaluru, India","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063041299","display_name":"Siva Sankara Sai Sanagapati","orcid":"https://orcid.org/0000-0003-1602-3269"},"institutions":[{"id":"https://openalex.org/I4819740","display_name":"Sri Sathya Sai Institute of Higher Learning","ror":"https://ror.org/05arzt710","country_code":"IN","type":"education","lineage":["https://openalex.org/I4819740"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Siva Sankara Sai Sanagapati","raw_affiliation_strings":["Sri Sathya Sai Institute of Higher Learning, Anantapur, India"],"raw_orcid":"https://orcid.org/0000-0003-1602-3269","affiliations":[{"raw_affiliation_string":"Sri Sathya Sai Institute of Higher Learning, Anantapur, India","institution_ids":["https://openalex.org/I4819740"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":1850,"currency":"USD","value_usd":1850},"apc_paid":{"value":1850,"currency":"USD","value_usd":1850},"fwci":2.4604,"has_fulltext":true,"cited_by_count":27,"citation_normalized_percentile":{"value":0.89058367,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":"7","issue":null,"first_page":"111727","last_page":"111735"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10522","display_name":"Medical Imaging Techniques and Applications","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2741","display_name":"Radiology, Nuclear Medicine and Imaging"},"field":{"id":"https://openalex.org/fields/27","display_name":"Medicine"},"domain":{"id":"https://openalex.org/domains/4","display_name":"Health Sciences"}},"topics":[{"id":"https://openalex.org/T10522","display_name":"Medical Imaging Techniques and Applications","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2741","display_name":"Radiology, Nuclear Medicine and Imaging"},"field":{"id":"https://openalex.org/fields/27","display_name":"Medicine"},"domain":{"id":"https://openalex.org/domains/4","display_name":"Health Sciences"}},{"id":"https://openalex.org/T10378","display_name":"Advanced MRI Techniques and Applications","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2741","display_name":"Radiology, Nuclear Medicine and Imaging"},"field":{"id":"https://openalex.org/fields/27","display_name":"Medicine"},"domain":{"id":"https://openalex.org/domains/4","display_name":"Health Sciences"}},{"id":"https://openalex.org/T10358","display_name":"Advanced Radiotherapy Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/3108","display_name":"Radiation"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8556180596351624},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8337610960006714},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6182493567466736},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.5945937633514404},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.5310968160629272},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.42602449655532837},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.41328752040863037},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"Hardware architecture","score":0.41243934631347656},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.41086822748184204},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.39774057269096375},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.39491403102874756},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3727961778640747},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3704500198364258},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.14687764644622803}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8556180596351624},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8337610960006714},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6182493567466736},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.5945937633514404},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.5310968160629272},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.42602449655532837},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.41328752040863037},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.41243934631347656},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.41086822748184204},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39774057269096375},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.39491403102874756},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3727961778640747},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3704500198364258},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.14687764644622803},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/access.2019.2932647","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2019.2932647","pdf_url":"https://ieeexplore.ieee.org/ielx7/6287639/8600701/08784190.pdf","source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:5d45e9bec6754a14a0b65d36de8c1719","is_oa":true,"landing_page_url":"https://doaj.org/article/5d45e9bec6754a14a0b65d36de8c1719","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Access, Vol 7, Pp 111727-111735 (2019)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1109/access.2019.2932647","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2019.2932647","pdf_url":"https://ieeexplore.ieee.org/ielx7/6287639/8600701/08784190.pdf","source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4099999964237213}],"awards":[],"funders":[{"id":"https://openalex.org/F4320320719","display_name":"Department of Science and Technology, Ministry of Science and Technology, India","ror":"https://ror.org/0101xrq71"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2965136699.pdf","grobid_xml":"https://content.openalex.org/works/W2965136699.grobid-xml"},"referenced_works_count":29,"referenced_works":["https://openalex.org/W1891900466","https://openalex.org/W1982167457","https://openalex.org/W1982527613","https://openalex.org/W1999320095","https://openalex.org/W2009464643","https://openalex.org/W2027915628","https://openalex.org/W2032474717","https://openalex.org/W2047673107","https://openalex.org/W2049633694","https://openalex.org/W2056045266","https://openalex.org/W2067830498","https://openalex.org/W2069629287","https://openalex.org/W2072949684","https://openalex.org/W2083089005","https://openalex.org/W2105007306","https://openalex.org/W2127854932","https://openalex.org/W2131615790","https://openalex.org/W2135260765","https://openalex.org/W2145522579","https://openalex.org/W2154009134","https://openalex.org/W2159940799","https://openalex.org/W2168242542","https://openalex.org/W2481351383","https://openalex.org/W2766485017","https://openalex.org/W3100733064","https://openalex.org/W4235599055","https://openalex.org/W4299563552","https://openalex.org/W6639525838","https://openalex.org/W6679942355"],"related_works":["https://openalex.org/W2058520863","https://openalex.org/W1519183141","https://openalex.org/W3151101169","https://openalex.org/W4252744808","https://openalex.org/W2142315955","https://openalex.org/W4383503138","https://openalex.org/W1659609664","https://openalex.org/W2075931580","https://openalex.org/W1593523093","https://openalex.org/W4214905828"],"abstract_inverted_index":{"The":[0,101,204,232],"major":[1],"requirements":[2],"of":[3,24,51,125,177,212],"a":[4,10,79,122,153,171,194,248],"good":[5],"tomographic":[6],"reconstruction":[7,21],"algorithm":[8,46,60],"are":[9,27,33,103,111,132],"reduction":[11],"in":[12,37,61,148,156,162],"radiation":[13],"dosage,":[14],"accurate":[15],"reconstruction,":[16],"detail":[17],"enhancement,":[18],"and":[19,110,118,220,230,244,270],"rapid":[20],"time.":[22,68],"Some":[23],"these":[25,52],"factors":[26],"covered":[28],"by":[29,90],"many":[30,50],"algorithms":[31],"but":[32],"not":[34,208],"collectively":[35],"addressed":[36],"one.":[38],"While":[39],"the":[40,75,84,149,166,178,181,199,213],"Maximum":[41],"Likelihood":[42],"Expectation":[43],"Maximization":[44],"(MLEM)":[45],"fares":[47],"well":[48,112],"on":[49,180,237,258],"factors,":[53],"it":[54],"is":[55,72,235],"difficult":[56],"to":[57,64,73,78,143,197,228,253],"apply":[58],"this":[59,163,221],"real-time":[62],"due":[63],"its":[65],"long":[66],"execution":[67,76,257],"Our":[69],"predetermined":[70],"goal":[71],"reduce":[74],"time":[77],"large":[80,123],"extent":[81],"so":[82],"that":[83],"MLEM's":[85],"advantages":[86],"can":[87],"be":[88],"leveraged":[89],"using":[91],"hardware":[92,108,175,202],"accelerators":[93,109],"such":[94],"as":[95,107],"Field":[96],"Programmable":[97],"Gate":[98],"Arrays":[99],"(FPGA).":[100],"FPGAs":[102,131,157],"becoming":[104],"especially":[105],"popular":[106],"known":[113],"for":[114,165,174],"their":[115],"programmability,":[116],"configurability,":[117],"massive":[119],"parallelism":[120],"through":[121],"number":[124],"Configurable":[126],"Logic":[127],"Blocks":[128],"(CLBs).":[129],"Although":[130],"extremely":[133],"versatile,":[134],"they":[135],"require":[136,209],"complex":[137],"languages":[138],"like":[139],"Verilog":[140],"or":[141],"VHDL":[142],"program":[144],"them,":[145],"incorporating":[146],"changes":[147,225],"design":[150,198,224],"level":[151],"at":[152,241],"later":[154],"stage":[155],"demands":[158],"increased":[159],"effort.":[160],"Here,":[161],"paper,":[164],"first":[167],"time,":[168],"we":[169,191,245],"present":[170,193],"parallel":[172,233],"structure":[173],"acceleration":[176,201],"MLEM":[179],"mammoth":[182],"Virtex":[183],"7":[184],"$VC$":[185],"709":[186],"FPGA.":[187],"Using":[188],"available":[189],"tools,":[190],"also":[192],"programming":[195],"flow":[196,206],"algorithmic":[200],"architecture.":[203,274],"proposed":[205],"does":[207],"prior":[210],"knowledge":[211],"traditionally":[214],"cumbersome":[215],"Hardware":[216],"Description":[217],"Languages":[218],"(HDLs)":[219],"makes":[222],"post":[223],"very":[226],"easy":[227],"incorporate":[229],"validate.":[231],"architecture":[234],"implemented":[236],"an":[238,254,259],"FPGA":[239],"operating":[240],"220":[242],"MHz":[243],"have":[246],"achieved":[247],"$288\\times":[249],"$":[250],"performance":[251],"compared":[252],"optimized":[255],"software":[256],"Intel":[260],"Xeon":[261],"workstation":[262],"with":[263],"12-cores":[264],"3.1":[265],"GHz":[266],"32":[267],"GB":[268],"RAM":[269],"12":[271],"MB":[272],"Cache":[273]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":7},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":7},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":3}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}