{"id":"https://openalex.org/W2946481338","doi":"https://doi.org/10.1109/access.2019.2911916","title":"Experimental Quantification of Hardware Requirements for FPGA-Based Reconfigurable PMUs","display_name":"Experimental Quantification of Hardware Requirements for FPGA-Based Reconfigurable PMUs","publication_year":2019,"publication_date":"2019-01-01","ids":{"openalex":"https://openalex.org/W2946481338","doi":"https://doi.org/10.1109/access.2019.2911916","mag":"2946481338"},"language":"en","primary_location":{"id":"doi:10.1109/access.2019.2911916","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2019.2911916","pdf_url":"https://ieeexplore.ieee.org/ielx7/6287639/8600701/08693773.pdf","source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://ieeexplore.ieee.org/ielx7/6287639/8600701/08693773.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5076271403","display_name":"Prottay M. Adhikari","orcid":"https://orcid.org/0000-0003-3688-8948"},"institutions":[{"id":"https://openalex.org/I165799507","display_name":"Rensselaer Polytechnic Institute","ror":"https://ror.org/01rtyzb94","country_code":"US","type":"education","lineage":["https://openalex.org/I165799507"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Prottay M. Adhikari","raw_affiliation_strings":["Department of Electrical Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY, USA"],"raw_orcid":"https://orcid.org/0000-0003-3688-8948","affiliations":[{"raw_affiliation_string":"Department of Electrical Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010219499","display_name":"Hossein Hooshyar","orcid":"https://orcid.org/0000-0002-6090-1674"},"institutions":[{"id":"https://openalex.org/I1335486098","display_name":"Electric Power Research Institute","ror":"https://ror.org/02dqztz06","country_code":"US","type":"nonprofit","lineage":["https://openalex.org/I1335486098"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hossein Hooshyar","raw_affiliation_strings":["Electric Power Research Institute, Palo Alto, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electric Power Research Institute, Palo Alto, CA, USA","institution_ids":["https://openalex.org/I1335486098"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038873326","display_name":"Luigi Vanfretti","orcid":"https://orcid.org/0000-0002-4125-1055"},"institutions":[{"id":"https://openalex.org/I165799507","display_name":"Rensselaer Polytechnic Institute","ror":"https://ror.org/01rtyzb94","country_code":"US","type":"education","lineage":["https://openalex.org/I165799507"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Luigi Vanfretti","raw_affiliation_strings":["Department of Electrical Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5076271403"],"corresponding_institution_ids":["https://openalex.org/I165799507"],"apc_list":{"value":1850,"currency":"USD","value_usd":1850},"apc_paid":{"value":1850,"currency":"USD","value_usd":1850},"fwci":0.9873,"has_fulltext":true,"cited_by_count":6,"citation_normalized_percentile":{"value":0.73338397,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":"7","issue":null,"first_page":"57527","last_page":"57538"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8059436678886414},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6947271227836609},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5638759136199951},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5376447439193726}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8059436678886414},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6947271227836609},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5638759136199951},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5376447439193726}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/access.2019.2911916","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2019.2911916","pdf_url":"https://ieeexplore.ieee.org/ielx7/6287639/8600701/08693773.pdf","source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:46b4c9a3b5f842a2bcd4e590b80f8710","is_oa":true,"landing_page_url":"https://doaj.org/article/46b4c9a3b5f842a2bcd4e590b80f8710","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Access, Vol 7, Pp 57527-57538 (2019)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1109/access.2019.2911916","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2019.2911916","pdf_url":"https://ieeexplore.ieee.org/ielx7/6287639/8600701/08693773.pdf","source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.6499999761581421}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2946481338.pdf","grobid_xml":"https://content.openalex.org/works/W2946481338.grobid-xml"},"referenced_works_count":24,"referenced_works":["https://openalex.org/W1553204923","https://openalex.org/W1668541361","https://openalex.org/W1757537413","https://openalex.org/W1991189698","https://openalex.org/W1998099960","https://openalex.org/W2019216467","https://openalex.org/W2023384057","https://openalex.org/W2027377403","https://openalex.org/W2058067234","https://openalex.org/W2112464699","https://openalex.org/W2129788823","https://openalex.org/W2133027790","https://openalex.org/W2150240500","https://openalex.org/W2171659032","https://openalex.org/W2496524656","https://openalex.org/W2558898687","https://openalex.org/W2601141468","https://openalex.org/W2609300502","https://openalex.org/W2736485710","https://openalex.org/W2766079102","https://openalex.org/W2783064047","https://openalex.org/W2784277736","https://openalex.org/W2900905581","https://openalex.org/W4231796025"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W2111241003","https://openalex.org/W2390279801","https://openalex.org/W4200391368","https://openalex.org/W2358668433","https://openalex.org/W2210979487","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841"],"abstract_inverted_index":{"Phasor":[0],"Measurement":[1],"Units":[2],"(PMUs)":[3],"are":[4],"becoming":[5],"intrinsic":[6],"components":[7],"of":[8,26,39,55],"modern":[9],"power":[10],"systems.":[11],"The":[12,86],"synchrophasor":[13],"estimation":[14],"algorithms":[15,41],"in":[16,103,132],"PMUs":[17,127],"pose":[18],"stringent":[19],"computational":[20],"demands,":[21],"which":[22],"makes":[23],"the":[24,37,53,94,110,122],"application":[25],"Field":[27],"Programmable":[28],"Gate":[29],"Arrays":[30],"(FPGA)":[31],"highly":[32],"attractive.":[33],"Previous":[34],"works":[35],"reported":[36],"implementation":[38,54,123],"PMU":[40,48,57,100],"on":[42,59,112],"specific":[43],"FPGA-targets":[44],"using":[45,63],"a":[46,76,98,115],"particular":[47],"design.":[49],"This":[50],"paper":[51],"explores":[52],"different":[56],"designs":[58],"multiple":[60],"FPGA":[61],"targets":[62],"Xilinx":[64],"and":[65,68,71,129],"NI":[66],"software":[67],"hardware":[69,84],"infrastructures":[70],"toolsets.":[72],"In":[73],"this":[74,118],"process,":[75],"metric":[77,87,119],"has":[78],"been":[79],"formulated":[80],"to":[81,96],"predict":[82],"FPGA-target":[83,92],"requirements.":[85],"allows":[88],"predicting":[89],"if":[90,134],"an":[91],"meets":[93],"needs":[95],"deploy":[97],"given":[99],"design":[101,106],"resulting":[102],"significant":[104],"engineering":[105],"time":[107,124],"savings.":[108],"Since":[109],"compilation/synthesis":[111],"FPGAs":[113],"is":[114],"time-consuming":[116],"job,":[117],"can":[120,130,137],"reduce":[121],"for":[125],"FPGA-based":[126],"drastically":[128],"help":[131],"determining":[133],"additional":[135],"functionalities":[136],"be":[138],"added.":[139]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":1}],"updated_date":"2026-05-06T08:25:59.206177","created_date":"2025-10-10T00:00:00"}
