{"id":"https://openalex.org/W2928221274","doi":"https://doi.org/10.1109/access.2019.2907976","title":"A Carry Lookahead Adder Based on Hybrid CMOS-Memristor Logic Circuit","display_name":"A Carry Lookahead Adder Based on Hybrid CMOS-Memristor Logic Circuit","publication_year":2019,"publication_date":"2019-01-01","ids":{"openalex":"https://openalex.org/W2928221274","doi":"https://doi.org/10.1109/access.2019.2907976","mag":"2928221274"},"language":"en","primary_location":{"id":"doi:10.1109/access.2019.2907976","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2019.2907976","pdf_url":"https://ieeexplore.ieee.org/ielx7/6287639/8600701/08676033.pdf","source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://ieeexplore.ieee.org/ielx7/6287639/8600701/08676033.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000603349","display_name":"Gongzhi Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I50760025","display_name":"Hangzhou Dianzi University","ror":"https://ror.org/0576gt767","country_code":"CN","type":"education","lineage":["https://openalex.org/I50760025"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Gongzhi Liu","raw_affiliation_strings":["Institute of Modern Circuits and Intelligent Information, Hangzhou Dianzi University, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Modern Circuits and Intelligent Information, Hangzhou Dianzi University, Hangzhou, China","institution_ids":["https://openalex.org/I50760025"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100300796","display_name":"Lijing Zheng","orcid":"https://orcid.org/0000-0002-4548-3048"},"institutions":[{"id":"https://openalex.org/I50760025","display_name":"Hangzhou Dianzi University","ror":"https://ror.org/0576gt767","country_code":"CN","type":"education","lineage":["https://openalex.org/I50760025"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lijing Zheng","raw_affiliation_strings":["Institute of Modern Circuits and Intelligent Information, Hangzhou Dianzi University, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Modern Circuits and Intelligent Information, Hangzhou Dianzi University, Hangzhou, China","institution_ids":["https://openalex.org/I50760025"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065201073","display_name":"Guangyi Wang","orcid":"https://orcid.org/0000-0002-6777-8234"},"institutions":[{"id":"https://openalex.org/I50760025","display_name":"Hangzhou Dianzi University","ror":"https://ror.org/0576gt767","country_code":"CN","type":"education","lineage":["https://openalex.org/I50760025"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Guangyi Wang","raw_affiliation_strings":["Institute of Modern Circuits and Intelligent Information, Hangzhou Dianzi University, Hangzhou, China"],"raw_orcid":"https://orcid.org/0000-0002-6777-8234","affiliations":[{"raw_affiliation_string":"Institute of Modern Circuits and Intelligent Information, Hangzhou Dianzi University, Hangzhou, China","institution_ids":["https://openalex.org/I50760025"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023450162","display_name":"Yiran Shen","orcid":"https://orcid.org/0000-0002-8340-6756"},"institutions":[{"id":"https://openalex.org/I50760025","display_name":"Hangzhou Dianzi University","ror":"https://ror.org/0576gt767","country_code":"CN","type":"education","lineage":["https://openalex.org/I50760025"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yiran Shen","raw_affiliation_strings":["Institute of Modern Circuits and Intelligent Information, Hangzhou Dianzi University, Hangzhou, China"],"raw_orcid":"https://orcid.org/0000-0002-8340-6756","affiliations":[{"raw_affiliation_string":"Institute of Modern Circuits and Intelligent Information, Hangzhou Dianzi University, Hangzhou, China","institution_ids":["https://openalex.org/I50760025"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108374861","display_name":"Yan Liang","orcid":null},"institutions":[{"id":"https://openalex.org/I50760025","display_name":"Hangzhou Dianzi University","ror":"https://ror.org/0576gt767","country_code":"CN","type":"education","lineage":["https://openalex.org/I50760025"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yan Liang","raw_affiliation_strings":["Institute of Modern Circuits and Intelligent Information, Hangzhou Dianzi University, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Modern Circuits and Intelligent Information, Hangzhou Dianzi University, Hangzhou, China","institution_ids":["https://openalex.org/I50760025"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":1850,"currency":"USD","value_usd":1850},"apc_paid":{"value":1850,"currency":"USD","value_usd":1850},"fwci":3.6327,"has_fulltext":true,"cited_by_count":61,"citation_normalized_percentile":{"value":0.9345425,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":99},"biblio":{"volume":"7","issue":null,"first_page":"43691","last_page":"43696"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.9275640249252319},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8122014403343201},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7800858616828918},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.66888427734375},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6589483618736267},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6439611911773682},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.577960193157196},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5270001292228699},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4949321150779724},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.46176427602767944},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.45891818404197693},{"id":"https://openalex.org/keywords/memistor","display_name":"Memistor","score":0.45421138405799866},{"id":"https://openalex.org/keywords/carry","display_name":"Carry (investment)","score":0.418123722076416},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3641219437122345},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2529509663581848},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.22034558653831482},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1846039593219757},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.13912123441696167},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.06737107038497925}],"concepts":[{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.9275640249252319},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8122014403343201},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7800858616828918},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.66888427734375},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6589483618736267},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6439611911773682},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.577960193157196},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5270001292228699},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4949321150779724},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.46176427602767944},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.45891818404197693},{"id":"https://openalex.org/C1895703","wikidata":"https://www.wikidata.org/wiki/Q6034938","display_name":"Memistor","level":4,"score":0.45421138405799866},{"id":"https://openalex.org/C2776299755","wikidata":"https://www.wikidata.org/wiki/Q432449","display_name":"Carry (investment)","level":2,"score":0.418123722076416},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3641219437122345},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2529509663581848},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.22034558653831482},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1846039593219757},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.13912123441696167},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.06737107038497925},{"id":"https://openalex.org/C10138342","wikidata":"https://www.wikidata.org/wiki/Q43015","display_name":"Finance","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/access.2019.2907976","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2019.2907976","pdf_url":"https://ieeexplore.ieee.org/ielx7/6287639/8600701/08676033.pdf","source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:3834e03fad6a4d179ddf83bf3bfeb941","is_oa":true,"landing_page_url":"https://doaj.org/article/3834e03fad6a4d179ddf83bf3bfeb941","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Access, Vol 7, Pp 43691-43696 (2019)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1109/access.2019.2907976","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2019.2907976","pdf_url":"https://ieeexplore.ieee.org/ielx7/6287639/8600701/08676033.pdf","source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8500000238418579}],"awards":[{"id":"https://openalex.org/G33949335","display_name":null,"funder_award_id":"61801154","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G4245132902","display_name":null,"funder_award_id":"61771176","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2928221274.pdf","grobid_xml":"https://content.openalex.org/works/W2928221274.grobid-xml"},"referenced_works_count":22,"referenced_works":["https://openalex.org/W2021383442","https://openalex.org/W2025674646","https://openalex.org/W2050639295","https://openalex.org/W2081729575","https://openalex.org/W2112181056","https://openalex.org/W2141071915","https://openalex.org/W2161330443","https://openalex.org/W2162651880","https://openalex.org/W2397892532","https://openalex.org/W2516467421","https://openalex.org/W2546925628","https://openalex.org/W2584094173","https://openalex.org/W2603064927","https://openalex.org/W2743001015","https://openalex.org/W2755261981","https://openalex.org/W2759700740","https://openalex.org/W2766113992","https://openalex.org/W2794418178","https://openalex.org/W2805005993","https://openalex.org/W2809226946","https://openalex.org/W4210830821","https://openalex.org/W6736339276"],"related_works":["https://openalex.org/W2098419840","https://openalex.org/W6024065","https://openalex.org/W1980349267","https://openalex.org/W24944685","https://openalex.org/W3010731809","https://openalex.org/W2063209251","https://openalex.org/W1965949818","https://openalex.org/W2502492371","https://openalex.org/W4224111724","https://openalex.org/W2140610743"],"abstract_inverted_index":{"Memristor-based":[0],"digital":[1],"logic":[2,24,30],"circuits":[3],"open":[4],"new":[5],"pathways":[6],"for":[7],"exploring":[8],"advanced":[9],"computing":[10],"architectures,":[11],"which":[12,53,102],"provide":[13],"a":[14],"promising":[15],"alternative":[16],"to":[17],"conventional":[18],"IC":[19],"technology.":[20,37],"In":[21],"several":[22],"memristor-based":[23],"design":[25,89],"methods,":[26],"the":[27,46,61,87,97],"memristor":[28],"ratioed":[29],"(MRL)":[31],"is":[32,55,63,68],"compatible":[33],"with":[34],"traditional":[35],"CMOS":[36],"Two":[38],"kinds":[39],"of":[40],"carry-lookahead":[41],"adders":[42],"(CLA)":[43],"based":[44,56],"on":[45,57],"hybrid":[47],"CMOS-memristor":[48],"structure":[49],"are":[50,78],"proposed,":[51],"within":[52],"one":[54,66],"MRL":[58,71],"logic,":[59],"and":[60,83,94,107],"other":[62],"an":[64],"improved":[65],"that":[67,86],"implemented":[69],"by":[70,80],"universal":[72],"gate":[73],"(MRLUG).":[74],"The":[75],"proposed":[76,88],"CLAs":[77],"verified":[79],"theoretical":[81],"analyses":[82],"simulations,":[84],"showing":[85],"method":[90],"requires":[91],"fewer":[92],"memristors":[93],"CMOSs":[95],"than":[96],"IMP-based":[98],"or":[99],"CMOS-based":[100],"CLAs,":[101],"means":[103],"smaller":[104],"circuit":[105],"size":[106],"lower":[108],"power":[109],"consumption.":[110]},"counts_by_year":[{"year":2026,"cited_by_count":4},{"year":2025,"cited_by_count":9},{"year":2024,"cited_by_count":10},{"year":2023,"cited_by_count":8},{"year":2022,"cited_by_count":11},{"year":2021,"cited_by_count":11},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":4}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
