{"id":"https://openalex.org/W2243815476","doi":"https://doi.org/10.1109/access.2016.2514398","title":"Design Flow and Characterization Methodology for Dual Mode Logic","display_name":"Design Flow and Characterization Methodology for Dual Mode Logic","publication_year":2015,"publication_date":"2015-01-01","ids":{"openalex":"https://openalex.org/W2243815476","doi":"https://doi.org/10.1109/access.2016.2514398","mag":"2243815476"},"language":"en","primary_location":{"id":"doi:10.1109/access.2016.2514398","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2016.2514398","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1109/access.2016.2514398","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036479426","display_name":"Viacheslav Yuzhaninov","orcid":null},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":true,"raw_author_name":"Viacheslav Yuzhaninov","raw_affiliation_strings":["Emerging Nanoscale Integrated Circuits and Systems Labs, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Emerging Nanoscale Integrated Circuits and Systems Labs, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032341525","display_name":"Itamar Levi","orcid":"https://orcid.org/0000-0002-5591-5799"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Itamar Levi","raw_affiliation_strings":["Emerging Nanoscale Integrated Circuits and Systems Labs, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Emerging Nanoscale Integrated Circuits and Systems Labs, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065902823","display_name":"Alexander Fish","orcid":"https://orcid.org/0000-0002-4994-1536"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Alexander Fish","raw_affiliation_strings":["Emerging Nanoscale Integrated Circuits and Systems Labs, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Emerging Nanoscale Integrated Circuits and Systems Labs, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5036479426"],"corresponding_institution_ids":["https://openalex.org/I13955877"],"apc_list":{"value":1850,"currency":"USD","value_usd":1850},"apc_paid":{"value":1850,"currency":"USD","value_usd":1850},"fwci":0.6024,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.73795842,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"3","issue":null,"first_page":"3089","last_page":"3101"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.7676547765731812},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6685614585876465},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.6055981516838074},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5839658379554749},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.5749621391296387},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5631802082061768},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.5314071774482727},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.47516128420829773},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4723031520843506},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.47095757722854614},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.445991575717926},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4347943067550659},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4188823997974396},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.370688259601593},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.2657654583454132},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.25120651721954346},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.19298261404037476},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18757829070091248},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1688506305217743},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11273518204689026}],"concepts":[{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.7676547765731812},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6685614585876465},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.6055981516838074},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5839658379554749},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5749621391296387},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5631802082061768},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.5314071774482727},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.47516128420829773},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4723031520843506},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.47095757722854614},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.445991575717926},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4347943067550659},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4188823997974396},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.370688259601593},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.2657654583454132},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.25120651721954346},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.19298261404037476},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18757829070091248},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1688506305217743},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11273518204689026},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/access.2016.2514398","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2016.2514398","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:6b16089309ae481dba0308f78da40429","is_oa":true,"landing_page_url":"https://doaj.org/article/6b16089309ae481dba0308f78da40429","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Access, Vol 3, Pp 3089-3101 (2015)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1109/access.2016.2514398","is_oa":true,"landing_page_url":"https://doi.org/10.1109/access.2016.2514398","pdf_url":null,"source":{"id":"https://openalex.org/S2485537415","display_name":"IEEE Access","issn_l":"2169-3536","issn":["2169-3536"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Access","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W203529317","https://openalex.org/W415832010","https://openalex.org/W566978853","https://openalex.org/W624234598","https://openalex.org/W966413371","https://openalex.org/W1484446818","https://openalex.org/W1505590927","https://openalex.org/W1518236483","https://openalex.org/W2007442413","https://openalex.org/W2009441606","https://openalex.org/W2025555754","https://openalex.org/W2037299409","https://openalex.org/W2038049046","https://openalex.org/W2057144541","https://openalex.org/W2108971405","https://openalex.org/W2130784115","https://openalex.org/W2150090234","https://openalex.org/W2159683499","https://openalex.org/W2159868837","https://openalex.org/W2167065655","https://openalex.org/W2167806561","https://openalex.org/W2520093650","https://openalex.org/W4230737292","https://openalex.org/W4234684342","https://openalex.org/W4236097879","https://openalex.org/W4243164749","https://openalex.org/W4244015912"],"related_works":["https://openalex.org/W2789662562","https://openalex.org/W2017528947","https://openalex.org/W1553855433","https://openalex.org/W1593362825","https://openalex.org/W1529529399","https://openalex.org/W2082591327","https://openalex.org/W2171918386","https://openalex.org/W2155174752","https://openalex.org/W2102499515","https://openalex.org/W2021357106"],"abstract_inverted_index":{"Recently,":[0],"the":[1,52,85,95,121,152],"dual":[2],"mode":[3],"logic":[4,90,142],"(DML)":[5],"family":[6],"was":[7],"introduced":[8],"as":[9,105],"a":[10,131],"superior":[11],"energy-delay":[12],"alternative":[13],"to":[14,27,43,119],"CMOS.":[15],"DML":[16,38,49,66,89,111,147],"gates":[17,67],"utilize":[18],"two":[19,70],"different":[20,71,138],"modes":[21],"of":[22,37,134],"operation,":[23],"dynamic":[24],"and":[25,56,78,99,107,126,141,144],"static,":[26],"selectively":[28],"achieve":[29],"either":[30],"high-performance":[31],"or":[32],"low-energy":[33],"operation.":[34],"Custom":[35],"designs":[36,136],"circuits":[39,50],"have":[40],"been":[41],"shown":[42],"be":[44,92],"very":[45,63],"efficient.":[46],"However,":[47],"implementing":[48],"using":[51],"standard":[53,96,153],"design":[54,97,122,148,154],"flow":[55,98,127,155],"Electronic":[57],"Design":[58],"Automation":[59],"(EDA)":[60],"tools":[61],"is":[62,116,149],"challenging,":[64],"since":[65],"operate":[68],"in":[69],"modes,":[72],"each":[73],"with":[74,94,137],"its":[75],"own":[76],"characteristics":[77],"operating":[79],"mechanisms.":[80],"This":[81],"paper":[82],"shows,":[83],"for":[84],"first":[86],"time,":[87],"that":[88,146],"can":[91],"compatible":[93],"optimized":[100],"by":[101],"various":[102],"tools,":[103],"such":[104],"synthesis":[106],"physical":[108],"design.":[109],"A":[110],"cell":[112],"library":[113],"characterization":[114],"methodology":[115,125],"also":[117],"proposed":[118],"support":[120],"flow.":[123],"The":[124],"were":[128],"verified":[129],"on":[130],"wide":[132],"variety":[133],"benchmark":[135],"gate":[139],"counts":[140],"depths,":[143],"show":[145],"efficient":[150],"under":[151],"restrictions.":[156]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1}],"updated_date":"2026-05-06T08:25:59.206177","created_date":"2025-10-10T00:00:00"}
