{"id":"https://openalex.org/W2146707697","doi":"https://doi.org/10.1109/54.748805","title":"Universal Test Interface for embedded-DRAM testing","display_name":"Universal Test Interface for embedded-DRAM testing","publication_year":1999,"publication_date":"1999-01-01","ids":{"openalex":"https://openalex.org/W2146707697","doi":"https://doi.org/10.1109/54.748805","mag":"2146707697"},"language":"en","primary_location":{"id":"doi:10.1109/54.748805","is_oa":false,"landing_page_url":"https://doi.org/10.1109/54.748805","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test of Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088167618","display_name":"Satoru Miyano","orcid":"https://orcid.org/0000-0002-1753-6616"},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"S. Miyano","raw_affiliation_strings":["Toshiba Corporation, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Toshiba Corporation, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109288187","display_name":"K. Sato","orcid":null},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Sato","raw_affiliation_strings":["Toshiba Corporation, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Toshiba Corporation, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5054222622","display_name":"Kenji Numata","orcid":"https://orcid.org/0000-0001-5029-3233"},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Numata","raw_affiliation_strings":["Toshiba Corporation, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Toshiba Corporation, Japan","institution_ids":["https://openalex.org/I1292669757"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1292669757"],"apc_list":null,"apc_paid":null,"fwci":0.6102,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.72499392,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"16","issue":"1","first_page":"53","last_page":"58"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9919000267982483,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.8303837776184082},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6589243412017822},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6471946239471436},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.5918824076652527},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.46919581294059753},{"id":"https://openalex.org/keywords/integration-testing","display_name":"Integration testing","score":0.4628625810146332},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3446986675262451},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3259637951850891},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3076007068157196},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.19801190495491028},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19625815749168396}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.8303837776184082},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6589243412017822},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6471946239471436},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.5918824076652527},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.46919581294059753},{"id":"https://openalex.org/C107683887","wikidata":"https://www.wikidata.org/wiki/Q782466","display_name":"Integration testing","level":3,"score":0.4628625810146332},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3446986675262451},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3259637951850891},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3076007068157196},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.19801190495491028},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19625815749168396},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/54.748805","is_oa":false,"landing_page_url":"https://doi.org/10.1109/54.748805","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test of Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1559277030","https://openalex.org/W1572309646","https://openalex.org/W2099236222","https://openalex.org/W2101840766","https://openalex.org/W2115988690","https://openalex.org/W2171874314","https://openalex.org/W2186147019","https://openalex.org/W4251744538","https://openalex.org/W6686729679"],"related_works":["https://openalex.org/W3120961607","https://openalex.org/W3148568549","https://openalex.org/W2098207691","https://openalex.org/W1979131826","https://openalex.org/W2370066713","https://openalex.org/W1984979050","https://openalex.org/W2978161533","https://openalex.org/W2379338802","https://openalex.org/W2360820851","https://openalex.org/W2125410430"],"abstract_inverted_index":{"Because":[0],"the":[1,15,34,38,50],"configurations":[2],"of":[3,33,40],"embedded":[4,54],"DRAM":[5,35,55],"macros":[6,41],"vary":[7],"for":[8,18],"each":[9,19],"product,":[10],"designers":[11],"normally":[12],"must":[13],"customize":[14],"test":[16],"circuitry":[17,25],"product.":[20],"The":[21,45],"authors":[22],"have":[23],"developed":[24],"(Universal":[26],"Test":[27,47],"Interface)":[28],"that":[29],"unifies":[30],"testing":[31],"regardless":[32],"configuration":[36],"and":[37],"number":[39],"on":[42],"a":[43],"chip.":[44],"Universal":[46],"Interface":[48],"alleviates":[49],"contradiction":[51],"inherent":[52],"in":[53],"testing.":[56]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
