{"id":"https://openalex.org/W2564831980","doi":"https://doi.org/10.1109/43.68414","title":"A fault model for PLAs","display_name":"A fault model for PLAs","publication_year":1991,"publication_date":"1991-01-01","ids":{"openalex":"https://openalex.org/W2564831980","doi":"https://doi.org/10.1109/43.68414","mag":"2564831980"},"language":"en","primary_location":{"id":"doi:10.1109/43.68414","is_oa":false,"landing_page_url":"https://doi.org/10.1109/43.68414","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112638134","display_name":"M. Ligthart","orcid":null},"institutions":[{"id":"https://openalex.org/I4210131230","display_name":"Philips (United States)","ror":"https://ror.org/03kw6wr76","country_code":"US","type":"company","lineage":["https://openalex.org/I4210122849","https://openalex.org/I4210131230"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"M.M. Ligthart","raw_affiliation_strings":["Philips Research Laboratories, Sunnyvale, CA, USA"],"affiliations":[{"raw_affiliation_string":"Philips Research Laboratories, Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I4210131230"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063391028","display_name":"R. Stans","orcid":null},"institutions":[{"id":"https://openalex.org/I4210122849","display_name":"Philips (Netherlands)","ror":"https://ror.org/02p2bgp27","country_code":"NL","type":"company","lineage":["https://openalex.org/I4210122849"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"R.J. Stans","raw_affiliation_strings":["Philips Research Laboratories, Eindhoven, Netherlands"],"affiliations":[{"raw_affiliation_string":"Philips Research Laboratories, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I4210122849"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5112638134"],"corresponding_institution_ids":["https://openalex.org/I4210131230"],"apc_list":null,"apc_paid":null,"fwci":1.0175,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.82047532,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"10","issue":"2","first_page":"265","last_page":"270"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/bridging","display_name":"Bridging (networking)","score":0.7755274772644043},{"id":"https://openalex.org/keywords/fault-model","display_name":"Fault model","score":0.6254847645759583},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5824275016784668},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5095820426940918},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4850980043411255},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2153720259666443},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.12130558490753174},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11602228879928589},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.08967763185501099},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.06689217686653137}],"concepts":[{"id":"https://openalex.org/C174348530","wikidata":"https://www.wikidata.org/wiki/Q188635","display_name":"Bridging (networking)","level":2,"score":0.7755274772644043},{"id":"https://openalex.org/C167391956","wikidata":"https://www.wikidata.org/wiki/Q1401211","display_name":"Fault model","level":3,"score":0.6254847645759583},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5824275016784668},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5095820426940918},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4850980043411255},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2153720259666443},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.12130558490753174},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11602228879928589},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.08967763185501099},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.06689217686653137}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/43.68414","is_oa":false,"landing_page_url":"https://doi.org/10.1109/43.68414","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1792710789","https://openalex.org/W1845681645","https://openalex.org/W1972369552","https://openalex.org/W1977537743","https://openalex.org/W1991643564","https://openalex.org/W1993775768","https://openalex.org/W1995428291","https://openalex.org/W2024467749","https://openalex.org/W2027257919","https://openalex.org/W2029173745","https://openalex.org/W2044076967","https://openalex.org/W2069681736","https://openalex.org/W2079863858","https://openalex.org/W2088013285","https://openalex.org/W2098112833","https://openalex.org/W2101428522","https://openalex.org/W2105296011","https://openalex.org/W2608590452","https://openalex.org/W4240197441","https://openalex.org/W4242412848","https://openalex.org/W4243398220","https://openalex.org/W4246995621"],"related_works":["https://openalex.org/W3040662175","https://openalex.org/W2053103169","https://openalex.org/W1807477017","https://openalex.org/W2916567375","https://openalex.org/W1159231614","https://openalex.org/W2998028709","https://openalex.org/W1530688075","https://openalex.org/W2006341133","https://openalex.org/W2522597310","https://openalex.org/W303980170"],"abstract_inverted_index":{"A":[0],"fault":[1,101],"model":[2,11,102],"for":[3,103],"programmable":[4],"logic":[5],"arrays":[6],"(PLAs)":[7],"is":[8,37,67],"discussed.":[9],"This":[10,98],"maps":[12],"realistic":[13],"failures":[14],"on":[15],"four":[16],"classes":[17],"of":[18,61,70,73,82],"faults:":[19],"multiple":[20,23,26,40,46,49,55,64,76,85,91,95,108,113],"stuck-at":[21,41,92],"faults,":[22,25,28,48,57],"bridging":[24,50,77,96],"crosspoint":[27,47,56,65,86,110],"and":[29,58,94,112],"faults":[30,42,51,66,87,93,111],"due":[31],"to":[32,45,54,105],"breaks":[33],"in":[34],"lines.":[35],"It":[36],"shown":[38],"that":[39],"are":[43,52],"equivalent":[44],"sub-equivalent":[53],"the":[59,71,80,100],"set":[60,72,81],"patterns":[62,74,83],"detecting":[63,75,84],"a":[68],"subset":[69],"faults.":[78,97],"Hence,":[79],"also":[88],"detects":[89],"all":[90],"reduces":[99],"PLAs":[104],"two":[106],"classes:":[107],"missing/extra":[109],"breaks.<":[114],"<ETX":[115],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[116],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">&gt;</ETX>":[117]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
